28.7.7 Interrupt Enable Set
Important: For PIC32CM LS00/LS60 Non-Secure accesses, read and
write accesses (RW*) are allowed only if the external interrupt x (EXTINTx) is set as
Non-Secure in the NONSEC register (NONSEC.EXTINTx bit).
This register allows the
user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR)
register.| Name: | INTENSET |
| Offset: | 0x10 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection, Mix-Secure |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| NSCHK | |||||||||
| Access | RW/RW/RW | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EXTINT15 | EXTINT14 | EXTINT13 | EXTINT12 | EXTINT11 | EXTINT10 | EXTINT9 | EXTINT8 | ||
| Access | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EXTINT7 | EXTINT6 | EXTINT5 | EXTINT4 | EXTINT3 | EXTINT2 | EXTINT1 | EXTINT0 | ||
| Access | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 31 – NSCHK Non-secure Check Interrupt Enable
Note: This bit field is only available for
PIC32CM LS00/LS60 and has no effect for
PIC32CM LE00.
Writing a '0'
to this bit has no effect.Writing a '1' to this bit will set the NSCHK Interrupt Enable bit.
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – EXTINT External Interrupt Enable
The bit x of EXTINT enables the interrupt associated with the EXTINTx pin.
Writing a '0' to bit x has no effect.
Writing a '1' to bit x will set the External Interrupt Enable bit x, which enables the external interrupt EXTINTx.
| Value | Description |
|---|---|
| 0 | The external interrupt x is disabled. |
| 1 | The external interrupt x is enabled. |