28.7.8 Interrupt Flag Status and Clear
Important: For PIC32CM LS00/LS60 Non-Secure accesses, read and
write accesses (RW*) are allowed only if the external interrupt x (EXTINTx) is set as
Non-Secure in the NONSEC register (NONSEC.EXTINTx bit).
| Name: | INTFLAG |
| Offset: | 0x14 |
| Reset: | 0x00000000 |
| Property: | Mix-Secure |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| NSCHK | |||||||||
| Access | RW/RW/RW | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EXTINT15 | EXTINT14 | EXTINT13 | EXTINT12 | EXTINT11 | EXTINT10 | EXTINT9 | EXTINT8 | ||
| Access | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EXTINT7 | EXTINT6 | EXTINT5 | EXTINT4 | EXTINT3 | EXTINT2 | EXTINT1 | EXTINT0 | ||
| Access | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | RW/RW*/RW | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 31 – NSCHK Non-secure Check Interrupt
Note: This bit field is only available for
PIC32CM LS00/LS60 and has no effect for
PIC32CM LE00.
The flag is
cleared by writing a '1' to it. This flag is set when write to either NONSEC and NSCHK
register and if the related bit of NSCHK is enabled and the related bit of NONSEC is
zero.Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – EXTINT External Interrupt
The flag bit x is cleared by writing a '1' to it.
This flag is set when EXTINTx pin matches the external interrupt sense configuration and will generate an interrupt request if INTENSET.EXTINT[x] is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the External Interrupt x flag.