44.12.5 Digital Frequency Locked Loop (DFLL48M) Characteristics

Table 44-44. DFLL48M Characteristics - Open Loop Mode⁽¹⁾⁽²⁾
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
f_OUT	Output frequency	IDFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 LDO Regulator mode	46.6	47.8	49	MHz
t_STARTUP	Start-up time	DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 f_OUTwithin 90 % of final value	-	8.3	9.1	μs

Note:

DFLL48 in open loop can be used only with LDO regulator
These are based on characterization

Table 44-45. DFLL48M Characteristics - Closed Loop Mode
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
f_CloseOUT	Average Output frequency	f_REF = XTAL, 32.768kHz, 100ppm DFLLMUL=1464	47.963	47.972	47.981	MHz
f_REF⁽²⁾⁽³⁾	Reference frequency		732	32768	33000	Hz
f_CloseJitter⁽¹⁾	Cycle to Cycle jitter	f_REF = XTAL, 32.768kHz, 100ppm DFLLMUL=1464	-	-	0.51	ns
t_LOCK⁽¹⁾	Lock time	f_REF = XTAL, 32.768kHz, 100ppm DFLLMUL=1464 DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 DFLLCTRL.BPLCKC = 1 DFLLCTRL.QLDIS = 0 DFLLCTRL.DDDIS = 1 DFLLMUL.FSTEP = 10	-	200	700	μs

Note:

These are based on characterization
To ensure that the device stays within the maximum allowed clock frequency, any reference clock for DFLL in close loop must be within a 2% error accuracy
These values are based on simulation. They are not covered by production test limits or characterization.

Table 44-46. Power Consumption⁽¹⁾
Symbol	Parameters	Conditions	Ta	Min.	Typ.	Max.	Units
I_DD	Power consumption,Open loop	DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512, V_DD=3.3V	Max. 85°C Typ. 25°C	-	286	-	µA
I_DD	Power consumption, Close loop	f_REF = 32.768kHz, V_DD=3.3V	Max. 85°C Typ. 25°C	-	362	-	µA

Note:

These values are based on characterization.

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