44.12.5 Digital Frequency Locked Loop (DFLL48M) Characteristics

Table 44-44. DFLL48M Characteristics - Open Loop Mode(1)(2)
Symbol Parameter Conditions Min. Typ. Max. Units
fOUT Output frequency IDFLLVAL.COARSE = DFLL48M COARSE CAL

DFLLVAL.FINE = 512

LDO Regulator mode

 46.6 47.8 49 MHz
tSTARTUP Start-up time DFLLVAL.COARSE = DFLL48M COARSE CAL

DFLLVAL.FINE = 512

fOUT within 90 % of final value

 - 8.3 9.1 μs
Note:
  1. DFLL48 in open loop can be used only with LDO regulator
  2. These are based on characterization
Table 44-45. DFLL48M Characteristics - Closed Loop Mode
Symbol Parameter Conditions Min. Typ. Max. Units
fCloseOUT Average Output frequency

fREF = XTAL, 32.768kHz, 100ppm

DFLLMUL=1464

 47.963 47.972 47.981 MHz
fREF(2)(3) Reference frequency 732 32768 33000 Hz
fCloseJitter(1) Cycle to Cycle jitter

fREF = XTAL, 32.768kHz, 100ppm

DFLLMUL=1464

 - - 0.51 ns
tLOCK(1) Lock time

fREF = XTAL, 32.768kHz, 100ppm
DFLLMUL=1464
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.DDDIS = 1
DFLLMUL.FSTEP = 10

 - 200 700 μs
Note:
  1. These are based on characterization
  2. To ensure that the device stays within the maximum allowed clock frequency, any reference clock for DFLL in close loop must be within a 2% error accuracy
  3. These values are based on simulation. They are not covered by production test limits or characterization.
Table 44-46. Power Consumption(1)
Symbol Parameters Conditions Ta Min. Typ. Max. Units
IDD Power consumption,Open loop

DFLLVAL.COARSE = DFLL48M COARSE CAL

DFLLVAL.FINE = 512, VDD=3.3V

 Max. 85°C Typ. 25°C - 286 - µA
Power consumption, Close loop fREF = 32.768kHz, VDD=3.3V - 362 -
Note:
  1. These values are based on characterization.