44.12.6 Digital Phase Lock Loop Characteristics

Table 44-47. Fractional Digital Phase Lock Loop (FDPLL96M) Characteristics
Symbol Parameter Conditions Min. Typ. Max. Units
FIN Input Clock Frequency - 32 - 2000 kHz
FOUT Output frequency PL0 48 - 48 MHz
PL2 48 - 96 MHz
JP(2) Period Jitter PL0, FIN=32kHz @ FOUT=48MHz - 1.9 5.0 %
PL2, FIN=32kHz @ FOUT=48MHz - 1.9 4.0
PL2, FIN=32kHz @ FOUT=96MHz - 3.3 7.0
PL0, FIN=2MHz @ FOUT=48MHz - 2.0 8.0
PL2, FIN=2MHz @ FOUT=48MHz - 2.0 4.0
PL2, FIN=2MHz @ FOUT=96MHz - 4.2 7.0
TLOCK(1) Lock Time

After startup, time to get lock signal,
FIN = 32kHz @ FOUT = 96MHz

- 1 2 ms

After startup, time to get lock signal,
FIN = 2MHz @ FOUT = 96MHz

 - 25 35 µs
Duty Duty Cycle(1) - 40 50 60 %
Note:
  1. These values are based on simulation. They are not covered by production test limits or characterization.
  2. These are based on characterization.
Table 44-48. Power Consumption(1)
Symbol Parameter Conditions Ta Min. Typ. Max. Units
IDD Current consumption Ck=48MHz (PL0), VDD =3.3V Max. 85°C Typ. 25°C - 454 548 µA
Ck=96MHz (PL2), VDD =3.3V - 934 1052
Note:
  1. These are based on characterization.