39.122 GMAC Interrupt Mask Register Priority Queue x

A read of this register returns the value of the receive complete interrupt mask.

A write to this register directly affects the state of the corresponding bit in the Interrupt Status Register, causing an interrupt to be generated if a 1 is written.

The following values are valid for all listed bit names of this register:

0: Corresponding interrupt is enabled.

1: Corresponding interrupt is disabled.

Name: GMAC_IMRPQx
Offset: 0x0640 + (x-1)*0x04 [x=1..2]
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
     HRESPROVR   
Access R/WR/W 
Reset 00 
Bit 76543210 
 TCOMPAHBRLEX  RXUBRRCOMP  
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bit 11 – HRESP System Bus Error

Bit 10 – ROVR Receive Overrun

Bit 7 – TCOMP Transmit Complete

Bit 6 – AHB Transmit Frame Corruption Due to System Bus Error

Bit 5 – RLEX Retry Limit Exceeded or Late Collision

Bit 2 – RXUBR RX Used Bit Read

Bit 1 – RCOMP Receive Complete