39.8 GMAC Transmit Buffer Queue Base Address Register

This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The Transmit Buffer Queue Base Address Register must be initialized before transmit is started through bit 9 of the Network Control Register. Once transmission has started, any write to the Transmit Buffer Queue Base Address Register is illegal and therefore ignored.

Note that due to clock boundary synchronization, it takes a maximum of four MCK cycles from the writing of the transmit start bit before the transmitter is active. Writing to the Transmit Buffer Queue Base Address Register during this time may produce unpredictable results.

Reading this register returns the location of the descriptor currently being accessed. Since the DMA handles two frames at once, this may not necessarily be pointing to the current frame being transmitted.

The descriptors must be aligned at 32-bit boundaries and the descriptors are read from memory using two individual non sequential accesses.

Name: GMAC_TBQB
Offset: 0x01C
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
 ADDR[29:22] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 ADDR[21:14] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 ADDR[13:6] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 ADDR[5:0]   
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bits 31:2 – ADDR[29:0] Transmit Buffer Queue Base Address

Written with the address of the start of the transmit queue.