39.5 GMAC DMA Configuration Register


Bit	31	30	29	28	27	26	25	24
								DDRP
Access								R/W
Reset								0


Bit	23	22	21	20	19	18	17	16
	DRBS[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
					TXCOEN	TXPBMS	RXBMS[1:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ESPA	ESMA		FBLDO[4:0]
Access	R/W	R/W		R/W	R/W	R/W	R/W	R/W
Reset	0	0		0	0	0	0	0

Bit 24 – DDRP DMA Discard Receive Packets

When set, the GMAC DMA automatically discards receive packets from the receiver packet buffer memory when no system memory resource is available.

When low, the received packets remain to be stored in the GMAC local memory packet buffer until a system memory buffer resource becomes available.

Bits 23:16 – DRBS[7:0] DMA Receive Buffer Size

DMA receive buffer size in system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data.

The value is defined in multiples of 64 bytes, thus a value of 0x01 corresponds to buffers of 64 bytes, 0x02 corresponds to 128 bytes etc.

For example:

– 0x02: 128 bytes

– 0x18: 1536 bytes (1 × max length frame/buffer)

– 0xA0: 10240 bytes (1 × 10K jumbo frame/buffer)

Note that this value should never be written as zero.

Bit 11 – TXCOEN Transmitter Checksum Generation Offload Enable

Transmitter IP, TCP and UDP checksum generation offload enable. When set, the transmitter checksum generation engine is enabled to calculate and substitute checksums for transmit frames. When clear, frame data is unaffected.

Bit 10 – TXPBMS Transmitter Packet Buffer Memory Size Select

Having this bit at zero halves the amount of memory used for the transmit packet buffer. This reduces the amount of memory used by the GMAC. It is important to set this bit to one if the full configured physical memory is available. The value in brackets below represents the size that would result for the default maximum configured memory size of 4 Kbytes.

Value	Name	Description
0	TWO_KB	Do not use top address bit (2 Kbytes).
1	FOUR_KB	Use full configured addressable space (4 Kbytes).

Bits 9:8 – RXBMS[1:0] Receiver Packet Buffer Memory Size Select

The default receive packet buffer size is 4 Kbytes. The table below shows how to configure this memory to FULL, HALF, QUARTER or EIGHTH of the default size.

Value	Name	Description
0	EIGHTH	4/8 Kbyte memory size
1	QUARTER	4/4 Kbytes memory size
2	HALF	4/2 Kbytes memory size
3	FULL	4 Kbytes memory size

Bit 7 – ESPA Endian Swap Mode Enable for Packet Data Accesses

When set, selects swapped endianism for system bus transfers. When clear, selects Little Endian mode.

Value	Name	Description
0	LITTLE_ENDIAN	Selects Little-endian endianism for system bus transfers.
1	BIG_ENDIAN	Selects swapped endianism for system bus transfers.

Bit 6 – ESMA Endian Swap Mode Enable for Management Descriptor Accesses