39.3 GMAC Network Status Register
Note: The register reset value is either
0x00000004 or 0x00000006 depending on the status of the GMDIO input pin.
| Name: | GMAC_NSR |
| Offset: | 0x008 |
| Reset: | see Note |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RXLPIS | IDLE | MDIO | |||||||
| Access | R | R | R | ||||||
| Reset | 0 | 1 | x |
Bit 7 – RXLPIS LPI Indication
Low power idle has been detected on receive. This bit is set when LPI is detected and reset when normal idle is detected. An interrupt is generated when the state of this bit changes.
Bit 2 – IDLE PHY Management Logic Idle
The PHY management logic is idle (i.e., has completed).
Bit 1 – MDIO MDIO Input Status
Returns status of the GMDIO pin.