46.10.45 SPI Receive Data Register

If FIFO is enabled (FLEX_SPI_CR.FIFOEN) and FLEX_SPI_FMR.RXRDYM = 0, see SPI Single Data Access for details.

Name: FLEX_SPI_RDR
Offset: 0x408
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
     PCS[3:0] 
Access RRRR 
Reset 0000 
Bit 15141312111098 
 RD[15:8] 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 RD[7:0] 
Access RRRRRRRR 
Reset 00000000 

Bits 19:16 – PCS[3:0] Peripheral Chip Select

In Host mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits are read as zero.

Note: When using Variable Peripheral Select mode (FLEX_SPI_MR.PS = 1), it is mandatory to set the FLEX_SPI_MR.WDRBT bit to 1 if the PCS field must be processed in FLEX_SPI_RDR.

Bits 15:0 – RD[15:0] Receive Data

Data received by the SPI Interface is stored in this register in a right-justified format. Unused bits are read as zero.