46.10.11 USART Interrupt Disable Register

For SPI-specific configurations, see USART Interrupt Disable Register (SPI_MODE).

For LIN-specific configurations, see USART Interrupt Disable Register (LIN_MODE).

The following configuration values are valid for all listed bit names of this register:

0: No effect

1: Disables the corresponding interrupt.

Name: FLEX_US_IDR
Offset: 0x20C
Reset: 
Property: Write-only

Bit 3130292827262524 
        MANE 
Access W 
Reset  
Bit 2322212019181716 
  CMP  CTSIC    
Access WW 
Reset  
Bit 15141312111098 
   NACK  ITERTXEMPTYTIMEOUT 
Access WWWW 
Reset  
Bit 76543210 
 PAREFRAMEOVRE  RXBRKTXRDYRXRDY 
Access WWWWWW 
Reset  

Bit 24 – MANE Manchester Error Interrupt Disable

Bit 22 – CMP Comparison Interrupt Disable

Bit 19 – CTSIC Clear to Send Input Change Interrupt Disable

Bit 13 – NACK Non Acknowledge Interrupt Disable

Bit 10 – ITER Max Number of Repetitions Reached Interrupt Disable

Bit 9 – TXEMPTY TXEMPTY Interrupt Disable

Bit 8 – TIMEOUT Timeout Interrupt Disable

Bit 7 – PARE Parity Error Interrupt Disable

Bit 6 – FRAME Framing Error Interrupt Disable

Bit 5 – OVRE Overrun Error Interrupt Disable

Bit 2 – RXBRK Receiver Break Interrupt Disable

Bit 1 – TXRDY TXRDY Interrupt Disable

Bit 0 – RXRDY RXRDY Interrupt Disable