36.20.37 Mode Register

This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.

Name:	HSMC_MODEx
Offset:	0x0710 + x*0x14 [x=0..3]
Reset:	0x10000003
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
			PS[1:0]
Access			R/W	R/W
Reset			0	1


Bit	23	22	21	20	19	18	17	16
				TDF_MODE	TDF_CYCLES[3:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
				DBW				BAT
Access				R/W				R/W
Reset				0				0


Bit	7	6	5	4	3	2	1	0
			EXNW_MODE[1:0]				WRITE_MODE	READ_MODE
Access			R/W	R/W			R/W	R/W
Reset			0	0			1	1

Bits 29:28 – PS[1:0] Page Size

If Page mode is enabled, this field indicates the size of the page in bytes.

Value	Name	Description
0	BYTE_4	4-byte page
1	BIT_8	8-byte page
2	BIT_16	16-byte page
3	BIT_32	32-byte page

Bit 20 – TDF_MODE TDF Optimization

Value	Description
0	TDF optimization disabled. The number of TDF Wait states is inserted before the next access begins.
1	TDF optimization enabled. The number of TDF Wait states is optimized using the setup period of the next read/write access.

Bits 19:16 – TDF_CYCLES[3:0] Data Float Time

This field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the read controlling signal. The SMC always provide one full cycle of bus turnaround after the TDF_CYCLES period. The external bus cannot be used by another chip select during TDF_CYCLES + 1 cycles. From 0 up to 15 TDF_CYCLES can be set.

Bit 12 – DBW Data Bus Width

Value	Name	Description
0	BIT_8	8-bit bus
1	BIT_16	16-bit bus

Bit 8 – BAT Byte Access Type

This field is used only if DBW defines a 16-bit data bus.

Value	Name	Description
0	BYTE_SELECT	Byte select access type: Write operation is controlled using NCS, NWE, NBS0, NBS1. Read operation is controlled using NCS, NRD, NBS0, NBS1.
1	BYTE_WRITE	Byte write access type: Write operation is controlled using NCS, NWR0, NWR1. Read operation is controlled using NCS and NRD.

Bits 5:4 – EXNW_MODE[1:0] NWAIT Mode

The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase Read and Write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be programmed for the read and write controlling signal.

Value	Name	Description
0	DISABLED	Disabled—The NWAIT input signal is ignored on the corresponding Chip Select.
1	–	Reserved
2	FROZEN	Frozen Mode—If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped.
3	READY	Ready Mode—The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high.