| Global |
Added content related to the SAMA5D27(T)-V/8GW(-SL3) device
General format update
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| Reference Document | New section |
| Configuration Summary |
Table 1-1: updates throughout
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| Signal Description |
Table 3-1: updated Timer/Counter rows
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| Standard Boot Strategies | Updated Boot Configuration |
| Matrix (H64MX/H32MX) |
MATRIX_PRBSx: corrected MPR field numbering
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| Special Function Registers (SFR) |
SFR_OHCIISR: restored RIS1 and RIS2 bits
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| Shutdown Controller (SHDWC) |
SHDW_MR: removed AUTOLPM
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| Real-Time Clock (RTC) |
Updated Waveform Generation, Figure 26-8, RTC Accurate Clock Calibration
RTC_TIMALR (DEFAULT_MODE): updated the AMPM bit description
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| Power
Management Controller (PMC) |
Main Crystal Oscillator Failure Detection: updated
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| Parallel Input/Output Controller (PIO) |
Updated Figure 33-2
Inputs: added Note
PIO_CFGRx: updated DIR description
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| Static Memory Controller (SMC) |
Embedded Characteristics: added ONFI compliance
content
Updated SMC Block Diagram, I/O Lines Description
Memory Connection for an 8-bit Data Bus, Memory Connection for a 16-bit Data Bus, Connection of 2 x 8-bit Devices on a 16-bit Bus: Byte Write
Option: added note
HSMC_SETUPx, HSMC_PULSEx: corrected register access to “Read/Write”
HSMC_SIGMA0: changed field name from SIGMA0 to SIGMA
HSMC_SIGMAx: corrected bitfield name from SIGMAx to
SIGMA
HSMC_MODEx: removed PS field
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| DMA
Controller (XDMAC) |
Updated Figure 37-5
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| Gigabit Ethernet MAC (GMAC) |
Embedded Characteristics, Media Access Controller, Jumbo Frames: updated support for jumbo frames
Updated PHY Interface
GMAC_RJFML: updated reset value
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| USB
Device High-Speed Port (UDPHS) |
Updated Transfer Without DMA, Power Management
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| Flexible Serial Communication Controller (FLEXCOM) |
Updated I/O Lines Description, Baud Rate Generator, Baud Rate in Synchronous Mode or SPI Mode, FIFO Overflow/Underflow Error, FIFO Overflow/Underflow Error, FIFO Overflow/Underflow Error
Modified content regarding multiple data reading in SPI Multiple Data Access, FLEX_SPI_RDR (FIFO_MULTI_DATA_8), FLEX_SPI_RDR (FIFO_MULTI_DATA_16)
FLEX_TWI_SR (DEFAULT_MODE), FLEX_TWI_SR (FIFO_ENABLED): index 17 now ‘reserved’
FLEX_TWI_SMBTR, FLEX_TWI_SWMR: added detail on WPEN
FLEX_SPI_MR: added LSBHALF
FLEX_US_FESR, FLEX_SPI_SR, FLEX_TWI_FSR: updated TXFPTEF and RXFPTEF
definitions
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| Secure Digital MultiMedia Card Controller (SDMMC) |
Updated Figure 50-4
SDMMC_CA0R: deleted note (2); updated bit descriptions with standard
“read-only” mention
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| Image
Sensor Controller (ISC) |
Updated White Balance (WB) Module
Rounding, Limiting and Packing (RLP) Module: updated
DATY10 table row
ISC_INTEN, ISC_INTDIS, ISC_INTMASK, ISC_INTSR: removed WPE
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| Controller Area Network (MCAN) |
Reworked Timestamping and Timestamp Generation
MCAN_TEST: updated RX bit description
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| Integrity Check Monitor (ICM) |
ICM_ISR: updated bit descriptions (cleared on read)
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| Advanced Encryption Standard Bridge (AESB) |
Register Summary: corrected register order
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| Advanced Encryption Standard (AES) |
Updated Start Modes, Encrypted Tweak Generation, Data Processing
XEX-based Tweaked-codebook Mode (XTS): updated auto-padding information
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| Triple Data Encryption Standard (TDES) |
Updated Block
Diagram
TC_BMR: updated TCxXCxS descriptions
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| Analog-to-Digital Controller (ADC) |
Updated Table 65-3
ADC_MR: updated reset value
ADC_SEQR2: corrected number of USCH fields (USCH12 is
now shown)
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| Electrical Characteristics |
DC Characteristics: updated introduction, added RthJB row in Table 66-2, updated VDDOSC row in Table 66-3
SPI Timing Extraction: updated Figure 66-18
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