4.5 Clocking Pins
(Ask a Question)Clock Conditioning Circuit (CCC) blocks, located at each corner of the RT PolarFire® SoC FPGAs, contain two PLLs and two DLLs that provide flexible on-chip and off-chip clock management and synthesis capabilities. CCCs are labeled according to their locations in the core. For example, the CCC located in the northeast corner is labeled as CCC_NE. For more information about clocking pins, see PolarFire Family Clocking Resources User Guide. Preferred clock inputs (CLKIN) are located on three sides of the device, with eight preferred clock inputs on the west side, twelve on the north side, and either 12 or 16 inputs on the south side, depending on the package.
The following table lists the clocking pin names and descriptions. For more information about
CCC pin voltage, see Table 4-2.
| Name | Description | When Unused |
|---|---|---|
| CCC_NW_PLL0_OUT[0:1] | Dedicated PLL output clock pins used to drive high-performance clocks in DDR3 and DDR4 applications located in the corners of RT PolarFire® SoC device to route the clocks to and from the PLLs and DLLs. | Do not connect (DNC) |
| CCC_NW_PLL1_OUT[0:1] | ||
| CCC_NE_PLL0_OUT[0:1] | ||
| CCC_NE_PLL1_OUT[0:1] | ||
| CCC_SE_PLL0_OUT[0:1] | ||
| CCC_SE_PLL1_OUT[0:1] | ||
| CCC_SW_PLL0_OUT[0:1] | ||
| CCC_SW_PLL1_OUT[0:1] | ||
| CCC_SE_CLKIN_S_[8:15] | Preferred clock inputs that connect external clock signals to the CCCs and the global clock network through low-latency paths. It is recommended to use these preferred clock inputs for connecting external clocks to the clock inputs of PLLs, DLLs and fabric logic. | DNC |
| CCC_SW_CLKIN_S_[0:3] | ||
| CCC_SW_CLKIN_W_[0:3] | ||
| CCC_NW_CLKIN_W_[4:7] | ||
| CCC_NW_CLKIN_N_[0:3] | ||
| CCC_NE_CLKIN_N_[8:11] | ||
| CLKIN_S_[4:7] | Preferred clock inputs directly routed to internal global buffers through MUXes. | DNC |
| CLKIN_N_[4:7] |
Note: Some of the preferred clock
inputs have connections to feedback clock input of the PLL/DLL present in the CCC. It is
required to choose a preferred clock input which has connection to the PLL reference clock
input for clock frequency synthesis. For preferred clock inputs connectivity to PLLs/DLLs
and global clock network, see PolarFire Family Clocking Resources User Guide.