4.6 Dedicated I/O Bank Pins

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JTAG, SPI and DEVRST_N signals share the same bank 3 supply and are not directly available to the fabric. SPI I/O are, however, dynamically switched over to be used by the fabric whenever the RT PolarFire® SoC controller is not using them. Dedicated I/O bank supplies must be powered up above their operational threshold and enabled before the RT PolarFire SoC controller negates the main power-on reset to the FPGA fabric. The following tables list the JTAG, SPI and DEVRST_N pin names and descriptions. Libero configures unused user I/O as input buffer disabled, output buffer tri-stated with weak pull-up. For more information about unused conditions, see RT PolarFire SoC FPGA Board Design User Guide.

The JTAG bank voltage can be set to operate at 1.8V, 2.5V or 3.3V. The following table lists the JTAG pins.

Table 4-7. JTAG Pins
Pin Names	Direction	Weak Pull-Up/Unused Condition	Description
TMS	Input	DNC	JTAG test mode select
TRSTB	Input	Must be connected to VDDI3 through a 1 kΩ resistor.	JTAG test reset. Must be held low during device operation.
TDI	Input	DNC	JTAG test data in
TCK	Input	Must be connected to VSS through a 10 kΩ resistor	JTAG test clock
TDO	Output	DNC	JTAG test data out

Note: If FPGA is in System Controller Suspend Mode and TRSTB is unused, either an external 1 kΩ pull-down resistor must be connected to TRSTB to override the weak internal pull-up, or TRSTB must be driven low from the external source.

The following table lists the device reset pin.

Table 4-8. Device Reset Pins
Name	Direction	Weak Pull-up	Description
DEVRST_N	Input	22 kΩ	Device reset (asserted low).

The following table lists the SPI interface pins.

Table 4-9. SPI Interface Pins
Name	Direction	Unused Condition	Description
SCK	Bidirectional	Connect to VSS through a 10 kΩ resistor	SPI clock
SS	Bidirectional	Connect to VSS through a 10 kΩ resistor	SPI slave select ¹
SDI	Input	Connect to VDDI3 through a 10 kΩ resistor	SDI input ¹
SDO	Output	DNC	SDO output ¹
SPI_EN	Input	Connect to VSS through a 10 kΩ resistor	SPI enable 0: SPI output tri-stated 1: Enabled Pulled up or down through a resistor or driven dynamically from an external source to enable or tri-state the SPI I/O.
IO_CFG_INTF	Input	Connect to VSS through a 10 kΩ resistor	SPI I/O configuration 0: SPI slave interface 1: SPI master interface Pulled up or down through a resistor or driven dynamically from an external source to indicate whether the shared SPI is a master or slave.

Note:

The SCK, SS, SDI, and SDO pins are shared between the system controller and the FPGA fabric. When the system controller’s SPI is enabled and configured as a master, the system controller hands over the control of the SPI to the fabric (after device power-up).

The following table lists the special pins.

Table 4-10. Special Pins
Name	Direction	Description	Unused Condition
NC	—	No connect pin. This pin indicates that it is not connected within the circuitry. NC pins can be driven by any voltage or can be left floating with no effect on the operation of the device.	—
DNC	—	Do not connect pin. DNC pins must not be connected to any signals on the PCB, and they must be left unconnected.	—
LPRB_A	Output	Specifies an internal signal for probing (oscilloscope-like feature). The two live probe I/O cells function as either a Live probe or User I/O (GPIO).	Libero-defined DNC
LPRB_B	Output		Libero-defined DNC
FF_EXIT_N	Input	Reserved	—
Shield Signal	Output	Shield signal is required for each DDR data byte signal. It must be driven with maximum drive strength to improve the signal integrity.	Only when DDR controller is in use