23.8.11 DFLLULP Read Request
| Name: | DFLLULPRREQ |
| Offset: | 0x1F |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RREQ | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 7 – RREQ Read Request
Writing a zero to this bit has no effect.
Writing a one to this bit requests synchronization of the DFLLULPDLY register with the current oscillator delay value and sets the Delay Busy bit in the Synchronization Busy register (DFLLULPSYNCBUSY.DELAY).
This bit is cleared automatically when synchronization is complete.