23.7 Register Summary


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	EVCTRL	7:0						TUNEINV	TUNEEI	CLKFAILEO
0x01 ... 0x03	Reserved
0x04	INTENCLR	7:0				OSC16MRDY			CLKFAIL	XOSCRDY
		15:8						DFLLULPNOLOCK	DFLLULPLOCK	DFLLULPRDY
		23:16					DPLLLDRTO	DPLLLTO	DPLLLCKF	DPLLLCKR
		31:24
0x08	INTENSET	7:0				OSC16MRDY			CLKFAIL	XOSCRDY
		15:8						DFLLULPNOLOCK	DFLLULPLOCK	DFLLULPRDY
		23:16					DPLLLDRTO	DPLLLTO	DPLLLCKF	DPLLLCKR
		31:24
0x0C	INTFLAG	7:0				OSC16MRDY			CLKFAIL	XOSCRDY
		15:8						DFLLULPNOLOCK	DFLLULPLOCK	DFLLULPRDY
		23:16					DPLLLDRTO	DPLLLTO	DPLLLCKF	DPLLLCKR
		31:24
0x10	STATUS	7:0				OSC16MRDY		CLKSW	CLKFAIL	XOSCRDY
		15:8						DFLLULPNOLOCK	DFLLULPLOCK	DFLLULPRDY
		23:16					DPLLLDRTO	DPLLLTO	DPLLLCKF	DPLLLCKR
		31:24
0x14	XOSCCTRL	7:0	ONDEMAND	RUNSTDBY		SWBACK	CFDEN	XTALEN	ENABLE
0x14	XOSCCTRL	15:8	STARTUP[3:0]				AMPGC	GAIN[2:0]
0x16	CFDPRESC	7:0						CFDPRESC[2:0]
0x17	Reserved
0x18	OSC16MCTRL	7:0	ONDEMAND	RUNSTDBY			FSEL[1:0]		ENABLE
0x19 ... 0x1B	Reserved
0x1C	DFLLULPCTRL	7:0	ONDEMAND	RUNSTDBY	DITHER	SAFE	BINSE	Reserved	ENABLE
0x1C	DFLLULPCTRL	15:8						DIV[2:0]
0x1E	DFLLULPDITHER	7:0		PER[2:0]				STEP[2:0]
0x1F	DFLLULPRREQ	7:0	RREQ
0x20	DFLLULPDLY	7:0	DELAY[7:0]
		15:8
		23:16
		31:24
0x24	DFLLULPRATIO	7:0	RATIO[7:0]
		15:8						RATIO[10:8]
		23:16
		31:24
0x28	DFLLULPSYNCBUSY	7:0					DELAY		ENABLE
		15:8
		23:16
		31:24
0x2C	DPLLCTRLA	7:0	ONDEMAND	RUNSTDBY					ENABLE
0x2D ... 0x2F	Reserved
0x30	DPLLRATIO	7:0	LDR[7:0]
		15:8					LDR[11:8]
		23:16					LDRFRAC[3:0]
		31:24
0x34	DPLLCTRLB	7:0			REFCLK[1:0]		WUF	LPEN	FILTER[1:0]
		15:8				LBYPASS		LTIME[2:0]
		23:16	DIV[7:0]
		31:24						DIV[10:8]
0x38	DPLLPRESC	7:0							PRESC[1:0]
0x39 ... 0x3B	Reserved
0x3C	DPLLSYNCBUSY	7:0					DPLLPRESC	DPLLRATIO	ENABLE
0x3D ... 0x3F	Reserved
0x40	DPLLSTATUS	7:0							CLKRDY	LOCK