23.8.2 Interrupt Enable Clear
| Name: | INTENCLR |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DPLLLDRTO | DPLLLTO | DPLLLCKF | DPLLLCKR | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DFLLULPNOLOCK | DFLLULPLOCK | DFLLULPRDY | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OSC16MRDY | CLKFAIL | XOSCRDY | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bit 19 – DPLLLDRTO DPLL Loop Divider Ratio Update Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the DPLL Loop Divider Ratio Update Complete Interrupt Enable bit, which disables the DPLL Loop Divider Ratio Update Complete interrupt.
| Value | Description |
|---|---|
| 0 | The DPLL Loop Divider Ratio Update Complete interrupt is disabled. |
| 1 | The DPLL Loop Divider Ratio Update Complete interrupt is enabled, and an interrupt request will be generated when the DPLL Loop Divider Ratio Update Complete Interrupt flag is set. |
Bit 18 – DPLLLTO DPLL Lock Timeout Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the DPLL Lock Timeout Interrupt Enable bit, which disables the DPLL Lock Timeout interrupt.
| Value | Description |
|---|---|
| 0 | The DPLL Lock Timeout interrupt is disabled. |
| 1 | The DPLL Lock Timeout interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Timeout Interrupt flag is set. |
Bit 17 – DPLLLCKF DPLL Lock Fall Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the DPLL Lock Fall Interrupt Enable bit, which disables the DPLL Lock Fall interrupt.
| Value | Description |
|---|---|
| 0 | The DPLL Lock Fall interrupt is disabled. |
| 1 | The DPLL Lock Fall interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Fall Interrupt flag is set. |
Bit 16 – DPLLLCKR DPLL Lock Rise Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the DPLL Lock Rise Interrupt Enable bit, which disables the DPLL Lock Rise interrupt.
| Value | Description |
|---|---|
| 0 | The DPLL Lock Rise interrupt is disabled. |
| 1 | The DPLL Lock Rise interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Rise Interrupt flag is set. |
Bit 10 – DFLLULPNOLOCK DFLLULP No Lock Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the DFLLULP No Lock interrupt Enable bit, which disables the DFLLULP No Lock interrupt.
| Value | Description |
|---|---|
| 0 | The DFLLULP No Lock is disabled. |
| 1 | The DFLLULP No Lock interrupt is enabled, and an interrupt request will be generated when the DFLLULP No Lock Interrupt flag is set. |
Bit 9 – DFLLULPLOCK DFLLULP Lock Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the DFLLULP Lock Interrupt Enable bit, which disables the DFLLULP Lock interrupt.
| Value | Description |
|---|---|
| 0 | The DFLLULP Lock interrupt is disabled. |
| 1 | The DFLLULP Lock interrupt is enabled, and an interrupt request will be generated when the DFLLULP Lock Interrupt flag is set. |
Bit 8 – DFLLULPRDY DFLLULP Ready interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the DFLLULP Ready Interrupt Enable bit, which disables the DFLLULP Ready interrupt.
| Value | Description |
|---|---|
| 0 | The DFLLULP Ready interrupt is disabled. |
| 1 | The DFLLULP Ready interrupt is enabled, and an interrupt request will be generated when the DFLLULP Ready Interrupt flag is set. |
Bit 4 – OSC16MRDY OSC16M Ready Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the OSC16M Ready Interrupt Enable bit, which disables the OSC16M Ready interrupt.
| Value | Description |
|---|---|
| 0 | The OSC16M Ready interrupt is disabled. |
| 1 | The OSC16M Ready interrupt is enabled, and an interrupt request will be generated when the OSC16M Ready Interrupt flag is set. |
Bit 1 – CLKFAIL Clock Failure Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the XOSC Clock Failure Interrupt Enable bit, which disables the XOSC Clock Failure interrupt.
| Value | Description |
|---|---|
| 0 | The XOSC Clock Failure interrupt is disabled. |
| 1 | The XOSC Clock Failure interrupt is enabled, and an interrupt request will be generated when the XOSC Clock Failure Interrupt flag is set. |
Bit 0 – XOSCRDY XOSC Ready Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the XOSC Ready Interrupt Enable bit, which disables the XOSC Ready interrupt.
| Value | Description |
|---|---|
| 0 | The XOSC Ready interrupt is disabled. |
| 1 | The XOSC Ready interrupt is enabled, and an interrupt request will be generated when the XOSC Ready Interrupt flag is set. |