23.8.9 DFLLULP Control
| Name: | DFLLULPCTRL |
| Offset: | 0x1C |
| Reset: | 0x0504 |
| Property: | PAC Write-Protection, Enable-Protected, Write-synchronized |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DIV[2:0] | |||||||||
| Access | R | R | R | R | R | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ONDEMAND | RUNSTDBY | DITHER | SAFE | BINSE | Reserved | ENABLE | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
Bits 10:8 – DIV[2:0] Division Factor
This field defines the division factor for the output frequency of the DFLLULP.
This value from production test, which depends on PL0 or PL2 mode, must be copied from the NVM software calibration row into the DFLLULPCTRL register by software.
The value must be changed before switching on a new Performance Level mode (PL0 or PL2).
These bits are not synchronized.
| Value | Name | Description |
|---|---|---|
| 0x0 | DIV1 | Frequency divided by 1 |
| 0x1 | DIV2 | Frequency divided by 2 |
| 0x2 | DIV4 | Frequency divided by 4 |
| 0x3 | DIV8 | Frequency divided by 8 |
| 0x4 | DIV16 | Frequency divided by 16 |
| 0x5 | DIV32 | Frequency divided by 32 |
| 0x6 - 0x7 | - | Reserved |
Bit 7 – ONDEMAND On Demand
The On Demand operation mode allows the oscillator to be enabled or disabled, depending on peripheral clock requests.
If the ONDEMAND bit has been previously written to '1', the oscillator will be running only when requested by a peripheral. If there is no peripheral requesting the oscillator’s clock source, the oscillator will be in a disabled state.
If On Demand is disabled, the oscillator will always be running when enabled.
In standby sleep mode, the On Demand operation is still active.
This bit is not Enable-Protected. This bit is not synchronized.Bit 6 – RUNSTDBY Run in Standby
This bit is not Enable-Protected. This bit is not synchronized
Bit 5 – DITHER Tuner Dither Mode
| Value | Description |
|---|---|
| 0 | The dither mode is disabled. |
| 1 | The dither mode is enabled |
Bit 4 – SAFE Tuner Safe Mode
| Value | Description |
|---|---|
| 0 | The clock output is not masked while binary search tuning is ongoing. |
| 1 | The clock output is masked while binary search tuning is ongoing (DFLLULPCTRL.BINSE = 1). |
Bit 3 – BINSE Binary Search Enable
| Value | Description |
|---|---|
| 0 | Binary search tuning is disabled. Maximum number of reference clock cycles to acquire lock is 256. |
| 1 | Binary search tuning is enabled. Maximum number of reference clock cycles to acquire lock is 8. |
Bit 2 – Reserved Must Be Set to 1
Bit 1 – ENABLE Enable
| Value | Description |
|---|---|
| 0 | The DFLLULP is disabled. |
| 1 | The DFLLULP is enabled. |