48.4 Power Consumption
The values in this section are measured values of power
consumption under the following conditions, except where noted:
- Operating
Conditions
- VDDIO = 3.3V or 1.8V
- CPU is running on Flash with required Wait states, as recommended in the NVM Characteristics section.
- Low-power cache is enabled
- BOD33 is disabled
- I/Os are configured with digital input trigger disabled (default Reset configuration)
- Oscillators
- XOSC (crystal oscillator) stopped
- XOSC32K (32.768 kHz crystal oscillator) running with external 32.768 kHz crystal
- When in active PL2 mode on FDPLL96M at 32 MHZ, DPLL is using XOSC32K as reference clock and running at 32 MHz
- When in Active mode on DFLLULP, the DFLLULP is configured in Closed Loop mode using XOSC32K as reference clock and MCLK.CTRLA.CKSEL = 1
Mode | Conditions | Regulator | PL | CPU Clock | Vcc | Ta | Typ. | Max. | Units |
---|---|---|---|---|---|---|---|---|---|
ACTIVE | COREMARK/FIBONACCI | LDO | PL0 | DFLLUP at 8 MHz | 1.8V | Max. at 125°C, Typ. at 25°C | 64.1 | 129 | uA/MHz |
3.3V | 64.4 | 131 | |||||||
OSC 8 MHz | 1.8V | 66.6 | 130 | ||||||
3.3V | 70.3 | 132 | |||||||
OSC 4 MHz | 1.8V | 74.1 | 203 | ||||||
3.3V | 77.8 | 206 | |||||||
PL2 | FDPLL96 at 32 MHz | 1.8V | 82.0 | 98 | |||||
3.3V | 82.5 | 99 | |||||||
DFLLULP at 32 MHz | 1.8V | 75.8 | 109 | ||||||
3.3V | 75.8 | 107 | |||||||
BUCK | PL0 | DFLLUP at 4.88 MHz | 1.8V | 44 | 103 | ||||
3.3V | 29.9 | 69 | |||||||
OSC 8 MHz | 1.8V | 43.8 | 84 | ||||||
3.3V | 32.1 | 58 | |||||||
OSC 4 MHz | 1.8V | 50.3 | 131 | ||||||
3.3V | 38.9 | 92 | |||||||
PL2 | FDPLL96 at 32 MHz | 1.8V | 59.9 | 70 | |||||
3.3V | 35.3 | 43 | |||||||
DFLLULP at 26.78 MHz | 1.8V | 55.8 | 80 | ||||||
3.3V | 33.7 | 48 | |||||||
WHILE1 | LDO | PL0 | DFLLUP at 8 MHz | 1.8V | 44.3 | 110 | |||
3.3V | 44.4 | 111 | |||||||
OSC 8 MHz | 1.8V | 47.6 | 111 | ||||||
3.3V | 50.1 | 113 | |||||||
OSC 4 MHz | 1.8V | 54.6 | 184 | ||||||
3.3V | 57.7 | 187 | |||||||
PL2 | FDPLL96 at 32 MHz | 1.8V | 56.9 | 79 | |||||
3.3V | 57.2 | 80 | |||||||
DFLLULP at 32 MHz | 1.8V | 50.8 | 72 | ||||||
3.3V | 51.0 | 72 | |||||||
ACTIVE | WHILE1 | BUCK | PL0 | DFLLUP at 4.88 MHz | 1.8V | Max. at 125°C, Typ. at 25°C | 32.4 | 90 | uA/MHz |
3.3V | 22.8 | 62 | |||||||
OSC 8 MHz | 1.8V | 32.2 | 73 | ||||||
3.3V | 25.3 | 51 | |||||||
WHILE1 | OSC 4 MHz | 1.8V | 38.4 | 121 | |||||
3.3V | 31.9 | 86 | |||||||
PL2 | FDPLL96 at 32 MHz | 1.8V | 41.5 | 55 | |||||
3.3V | 24.6 | 34 | |||||||
DFLLULP at 26.78 MHz | 1.8V | 38.3 | 58 | ||||||
3.3V | 23.1 | 36 | |||||||
IDLE | -- | LDO | PL0 | DFLLUP at 8 MHz | 1.8V | 16.0 | 81 | ||
3.3V | 16.2 | 82 | |||||||
OSC 8 MHz | 1.8V | 19.8 | 82 | ||||||
3.3V | 22.0 | 85 | |||||||
OSC 4 MHz | 1.8V | 26.2 | 152 | ||||||
3.3V | 29.2 | 157 | |||||||
PL2 | FDPLL96 at 32 MHz | 1.8V | 20.3 | 54 | |||||
3.3V | 20.4 | 54 | |||||||
DFLLULP at 32 MHz | 1.8V | 14.3 | 32 | ||||||
3.3V | 14.4 | 33 | |||||||
BUCK | PL0 | DFLLUP at 4.88 MHz | 1.8V | 15.1 | 68 | ||||
3.3V | 12.3 | 48 | |||||||
OSC 8 MHz | 1.8V | 15.5 | 55 | ||||||
3.3V | 15.2 | 40 | |||||||
OSC 4 MHz | 1.8V | 21.3 | 100 | ||||||
3.3V | 21.6 | 73 | |||||||
PL2 | FDPLL96 at 32 MHz | 1.8V | 14.9 | 30 | |||||
3.3V | 9.1 | 19 | |||||||
DFLLULP at 26.78 MHz | 1.8V | 11.2 | 26 | ||||||
3.3V | 7.2 | 17 |
Mode | Conditions | Regulator Mode | Vcc | Ta | Typ. | Max. | Units | ||
---|---|---|---|---|---|---|---|---|---|
STANDBY | All 16kB RAM retained, PDSW domain in active state | LPEFF Disable | 1,8V | 25°C | 1.3 | 3.5 | µA | ||
125°C | 121.7 | 304.8 | |||||||
LPEFF Enable | 3,3V | 25°C | 1.1 | 3.0 | |||||
125°C | 74.5 | 282.6 | |||||||
BUCK in standby PL0 (VREG.RUNSTDBY=1 and VREG.STDBYPL0=1) | 1,8V | 25°C | 1.2 | 2.9 | |||||
125°C | 78.0 | 188.7 | |||||||
3,3V | 25°C | 1.1 | 2.2 | ||||||
125°C | 50.9 | 122.9 | |||||||
All 16kB RAM retained, PDSW domain in retention | LPEFF Disable | 1,8V | 25°C | 0.6 | 1.1 | ||||
125°C | 27.1 | 81.0 | |||||||
LPEFF Enable | 3,3V | 25°C | 0.5 | 1.0 | |||||
125°C | 23.1 | 52.8 | |||||||
BUCK in standby PL0 (VREG.RUNSTDBY=1 and VREG.STDBYPL0=1) | 1,8V | 25°C | 0.8 | 1.1 | |||||
125°C | 23.0 | 53.7 | |||||||
3,3V | 25°C | 0.8 | 1.5 | ||||||
125°C | 17.3 | 37.6 | |||||||
12 kB RAM retained, PDSW domain in retention | LPEFF Disable | 1,8V | 25°C | 0.6 | 1.1 | ||||
125°C | 25.5 | 73.7 | |||||||
LPEFF Enable | 3,3V | 25°C | 0.5 | 1.0 | |||||
125°C | 21.6 | 48.8 | |||||||
Buck in standby PL0 (VREG.RUNSTDBY=1 and VREG.STDBYPL0=1) | 1,8V | 25°C | 0.7 | 1.1 | |||||
125°C | 21.5 | 50.5 | |||||||
3,3V | 25°C | 0.8 | 1.5 | ||||||
125°C | 16.4 | 35.4 | |||||||
STANDBY | 8kB RAM retained, PDSW domain in retention | LPEFF Disable | 1,8V | 25°C | 0.5 | 1.0 | µA | ||
125°C | 23.8 | 67.1 | |||||||
LPEFF Enable | 3,3V | 25°C | 0.5 | 0.9 | |||||
125°C | 20.2 | 45.4 | |||||||
BUCK in standby PL0 (VREG.RUNSTDBY=1 and VREG.STDBYPL0=1) | 1,8V | 25°C | 0.7 | 1.0 | |||||
125°C | 19.9 | 46.5 | |||||||
3,3V | 25°C | 0.7 | 1.4 | ||||||
125°C | 15.5 | 33.2 | |||||||
STANDBY | 4kB RAM retained, PDSW domain in retention | LPEFF Disable | 1,8V | 25°C | 0.5 | 0.9 | μA | ||
125°C | 22.0 | 58.9 | |||||||
LPEFF Enable | 3,3V | 25°C | 0.5 | 0.9 | |||||
125°C | 18.7 | 41.5 | |||||||
BUCK in standby PL0 (VREG.RUNSTDBY=1 and VREG.STDBYPL0=1) | 1,8V | 25°C | 0.7 | 1.0 | |||||
125°C | 18.4 | 42.7 | |||||||
3,3V | 25°C | 0.8 | 1.5 | ||||||
125°C | 14.6 | 31.0 | |||||||
4kB RAM retained, PDSW domain in retention and RTC running on XOSC32k | LPEFF Disable | 1,8V | 25°C | 0.9 | 1.3 | ||||
125°C | 22.6 | 59.8 | |||||||
LPEFF Enable | 3,3V | 25°C | 0.8 | 1.2 | |||||
125°C | 19.3 | 42.1 | |||||||
BUCK in standby PL0 (VREG.RUNSTDBY=1 and VREG.STDBYPL0=1) | 1,8V | 25°C | 1.0 | 1.3 | |||||
125°C | 19.0 | 43.3 | |||||||
3,3V | 25°C | 1.1 | 1.7 | ||||||
125°C | 15.2 | 31.6 | |||||||
OFF | 1,8V | 25°C | 34.6 | 54.4 | nA | ||||
125°C | 4385.0 | 8291.5 | |||||||
3,3V | 25°C | 61.2 | 89.1 | ||||||
125°C | 5489.5 | 10564.7 |