16.12.10 Configuration

Name: CFG
Offset: 0x001C
Reset: 0x00000002
Property: PAC Write-Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
     DCCDMALEVEL[1:0]LQOS[1:0] 
Access RWRWRWRW 
Reset 0002 

Bits 3:2 – DCCDMALEVEL[1:0] DMA TriggerLevel

0x0X: DCC1 trigger is the image of STATUSB.DCC1D, this signals to the DMA that a data is available for read, this is the correct configuration for a channel that reads DCC1.

0x1X: DCC1 trigger is the image of STATUSB.DCC1D inverted, this signals to the DMA that DCC1 is ready for write, this is the correct configuration for a channel that writes DCC1

0xX0: DCC0 trigger is the image of STATUSB.DCC0D, this signals to the DMA that a data is available for read, this is the correct configuration for a channel that reads DCC0.

0xX1: DCC0 trigger is the image of STATUSB.DCC0D inverted, this signals to the DMA that DCC0 is ready for write, this is the correct configuration for a channel that writes DCC0

Bits 1:0 – LQOS[1:0] Latency Quality Of Service

Defines the latency quality of service required when accessing the RAM:

0: Background Transfers

1: Bandwidth Sensitive

2: Latency sensitive

3: Latency critical