16.12.13 CoreSight ROM Table Entry 0
| Name: | ENTRY0 |
| Offset: | 0x1000 |
| Reset: | 0x9F0FC002 - x determined by Debug Access Level (DAL) |
| Property: | PAC Write Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ADDOFF[19:12] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | x | x | x | x | x | x | x | x | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ADDOFF[11:4] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | x | x | x | x | x | x | x | x | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ADDOFF[3:0] | |||||||||
| Access | R | R | R | R | |||||
| Reset | x | x | x | x | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FMT | EPRES | ||||||||
| Access | R | R | |||||||
| Reset | 1 | x |
Bits 31:12 – ADDOFF[19:0] Address Offset
The base address of the component, relative to the base address of this ROM table.
Bit 1 – FMT Format
Always reads as '1', indicating a 32-bit ROM table.
Bit 0 – EPRES Entry Present
This bit indicates whether an entry is present at this location in the ROM table.
This bit is set at power-up if the Debug Access Level is different from DAL0, indicating that the entry is present.
This bit is cleared at power-up if the Debug Access Level is DAL0, indicating that the entry is not present.