39.3.1 Supply Voltage

Table 39-1. 
PIC16LF18455/56 only
Standard Operating Conditions (unless otherwise stated)
Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions
Supply Voltage
D002 VDD

1.8

—

3.6

V

 FOSC ≤ 16 MHz

2.5

—

3.6

V

 FOSC > 16 MHz
RAM Data Retention(1)
D003 VDR 1.5

—

—

V

 Device in Sleep mode
Power-on Reset Release Voltage(2)
D004 VPOR

—

 1.6

—

V

 BOR or LPBOR disabled(3)
Power-on Reset Rearm Voltage(2)
D005 VPORR

—

 0.8

—

V

 BOR or LPBOR disabled(3)
VDD Rise Rate to ensure internal Power-on Reset signal(2)
D006 SVDD 0.05

—

—

 V/ms BOR or LPBOR disabled(3)

† - Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note:
  1. This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
  2. See the following figure, POR and POR REARM with Slow Rising VDD.
  3. Please see 39.4.5 Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-out Reset and Low-Power Brown-out Reset Specifications for BOR and LPBOR trip point information.
PIC16F18455/56 only
Standard Operating Conditions (unless otherwise stated)
Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions
Supply Voltage
D002 VDD

2.3

—

5.5

V

 FOSC ≤ 16 MHz

2.5

—

5.5

V

 FOSC > 16 MHz
RAM Data Retention(1)
D003 VDR 1.7

—

—

V

 Device in Sleep mode
Power-on Reset Release Voltage(2)
D004 VPOR

—

 1.6

—

V

 BOR or LPBOR disabled(3)
Power-on Reset Rearm Voltage(2)
D005 VPORR

—

 1.5

—

V

 BOR or LPBOR disabled(3)
VDD Rise Rate to ensure internal Power-on Reset signal(2)
D006 SVDD 0.05

—

—

 V/ms BOR or LPBOR disabled(3)

† - Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note:
  1. This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
  2. See the following figure, POR and POR REARM with Slow Rising VDD.
  3. Please see 39.4.5 Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-out Reset and Low-Power Brown-out Reset Specifications for BOR and LPBOR trip point information.
Figure 39-3. POR and POR Rearm with Slow Rising VDD
Note:
  1. When NPOR is low, the device is held in Reset.