4.7.2 CONFIG2

Supervisor

Note:
  1. The DEBUG bit in the Configuration Word 2 is managed automatically by device development tools, including debuggers and programmers. For normal device operation, this bit needs to be maintained as a ‘1’.
  2. See the VBOR parameter in the “Electrical Specifications” chapter for specific trip point voltages.
Name: CONFIG2
Address: 0x8008

Configuration Word 2

Bit 15141312111098 
   DEBUGSTVRENPPS1WAYZCDBORV 
Access R/PR/PR/PR/PR/PU 
Reset 111111 
Bit 76543210 
 BOREN[1:0]LPBORENPWRTS[1:0]MCLRE 
Access R/PR/PR/PUUR/PR/PR/P 
Reset 11111111 

Bit 13 – DEBUG  Debugger Enable bit(1)

ValueDescription
1 Background debugger disabled
0 Background debugger enabled

Bit 12 – STVREN Stack Overflow/Underflow Reset Enable bit

ValueDescription
1 Stack Overflow or Underflow will cause a Reset
0 Stack Overflow or Underflow will not cause a Reset

Bit 11 – PPS1WAY PPSLOCKED bit One-Way Set Enable bit

ValueDescription
1 The PPSLOCKED bit can be cleared and set only once; the PPS registers remain locked after one clear/set cycle
0 The PPSLOCKED bit can be set and cleared repeatedly (subject to the unlock sequence)

Bit 10 – ZCD ZCD Control bit

ValueDescription
1 ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of the ZCDCON register.
0 ZCD always enabled, the ZCDSEN bit is ignored

Bit 9 – BORV  Brown-out Reset Voltage Selection bit(2)

ValueDescription
1 Brown-out Reset voltage (VBOR) set to lower trip point level
0 Brown-out Reset voltage (VBOR) set to higher trip point level

Bits 7:6 – BOREN[1:0] Brown-out Reset Enable bits

When enabled, Brown-out Reset Voltage (VBOR) is set by the BORV bit

ValueDescription
11 Brown-out Reset enabled, the SBOREN bit is ignored
10 Brown-out Reset enabled while running, disabled in Sleep; the SBOREN is ignored
01 Brown-out Reset enabled according to SBOREN
00 Brown-out Reset disabled

Bit 5 – LPBOREN Low-Power BOR Enable bit

ValueDescription
1 Low-Power Brown-out Reset is disabled
0 Low-Power Brown-out Reset is enabled

Bits 2:1 – PWRTS[1:0] Power-up Timer Selection bits

ValueDescription
11 PWRT disabled
10 PWRT set at 64 ms
01 PWRT set at 16 ms
00 PWRT set at 1 ms

Bit 0 – MCLRE  Master Clear (MCLR) Enable bit

ValueNameDescription
If LVP = 1 RE3 pin function is MCLR (it will reset the device when driven low)
1 If LVP = 0 MCLR pin is MCLR (it will reset the device when driven low)
0 If LVP = 0 MCLR pin function is port defined function
The DEBUG bit in the Configuration Word 2CONFIG2 is managed automatically by device development tools, including debuggers and programmers. For normal device operation, this bit needs to be maintained as a ‘1’. See the VBOR parameter in the “Electrical Specifications” chapter for specific trip point voltages.