12.1.1 Doze Operation
The Doze operation is illustrated in Figure 12-1. For this example:
As with normal operation, the program memory fetches for the next instruction cycle. The instruction clocks to the peripherals continue throughout.
![](GUID-D16E3A91-AFDE-4FDB-A3FB-7758BCF63A0A-low.png)
Note:
- Multicycle instructions are executed to completion before fetching 0004h.
- If the prefetched instruction clears GIE, the ISR will not occur, but DOZEN is still cleared and the CPU will resume execution at full speed.