8.6.1 OSCCON1

Oscillator Control Register1
Note:
  1. The default value (f) is determined by the CONFIG1[RSTOSC] Configuration bits.
  2. If NOSC is written with a reserved value, the operation is ignored and NOSC is not written.
  3. When CONFIG1[CSWEN] = 0, this register is read-only and cannot be changed from the POR value.
  4. When NOSC = 110 (HFINTOSC 1 MHz), the NDIV bits will default to ‘0010’ upon Reset; for all other NOSC settings the NDIV bits will default to ‘0000’ upon Reset.
  5. EXTOSC configured by CONFIG1[FEXTOSC].
  6. HFINTOSC frequency is set with the FRQ bits of the OSCFRQ register.
Name: OSCCON1
Address: 0x88D

Bit 76543210 
  NOSC[2:0]NDIV[3:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset fffqqqq 

Bits 6:4 – NOSC[2:0]  New Oscillator Source Request bits(1,2,3)

The setting requests a source oscillator and PLL combination per Table 8-2.

Table 8-2. NOSC Bit Settings
NOSC[2:0] Clock Source
111 EXTOSC(5)
110 HFINTOSC(6)
101 LFINTOSC
100 SOSC
011 Reserved
010 EXTOSC + 4x PLL(5)
001 HFINTOSC + 2x PLL(6)
000 Reserved

Bits 3:0 – NDIV[3:0]  New Divider Selection Request bits(2,3,4)

The setting determines the new postscaler division ratio per Table 8-1.

Table 8-1. NDIV Bit Settings
NDIV[3:0] Clock Divider
1111-1010 Reserved
1001 512
1000 256
0111 128
0110 64
0101 32
0100 16
0011 8
0010 4
0001 2
0000 1
The default value (f) is determined by the CONFIG1[RSTOSC] Configuration bits. If NOSC is written with a reserved value, the operation is ignored and NOSC is not written. When CONFIG1[CSWEN] = 0, this register is read-only and cannot be changed from the POR value. When NOSC = 110 (HFINTOSC 1 MHz), the NDIV bits will default to ‘0010’ upon Reset; for all other NOSC settings the NDIV bits will default to ‘0000’ upon Reset. EXTOSC configured by CONFIG1[FEXTOSC]. HFINTOSC frequency is set with the FRQ bits of the OSCFRQ register.