2.3.1.2 Fabric Interface

Use this field to configure the bus standard (AXI or AHBLite) and interface (Master only, Slave only, or both) for the PCIe protocol.

In PCIe mode, the SerDes block can act as an AXI or AHBLite master.

You must instantiate a COREAXI or CoreAHBLite bus into the SmartDesign Canvas and then connect the Master and/or Slave Bus Interface (BIF) of the SerDes to the Master and/or Slave BIF of the COREAXI bus or CoreAHBLite bus.