2.3.1.3 Base Address Registers

The individual fields of the six Base address registers (Bar 0 to Bar 5) can be configured as follows:

• Width—The width on even registers can be 32 bit or 64 bit. If an even register is set to 64 bits wide, the subsequent (odd) register serves as the upper half of 64 bits. The width of odd registers is restricted to 32 bits.
• Size—The ranges from 4 KB to 2 GB when width is 32 bit. Some devices support only up to 1 GB. When the width is 64 bit, the size can range from 2 KB to 16 KB.
  Note: M2S150/M2GL150, M2S090/M2GL090, and M2S060/M2GL060 devices support 2 GB; all other devices support 1GB.
  See your device datasheet (IGLOO2 FPGA and SmartFusion2 SoC FPGA Datasheet) for more information.
• Prefetchable—Enabled only on even registers with 64 bit width.