8.8.1 Behavioral Simulation

Use the following procedures to perform a behavioral simulation of an Actel design. For more information about performing simulation with SpeedWave, see the Innoveda documentation:

1. Select your Actel project in Project Manager. If you have not created your project, go to Project Setup for the procedure.
2. Open the HDL Manager. This displays the HDL manager dialog box.
3. Open a project HDL workspace (.hws) file. Choose the Open command from the File menu. Select an .hws file and click the Open button in the Open dialog box.
4. Analyze your behavioral VHDL design files and testbench. Select the user library icon in the VHDL User Libraries section of the VHDL View window. Choose the Add Source Files command from the Library menu. The Assign Source Files dialog box is displayed. Select the behavioral VHDL and testbench files from the VHDL Source File Name window and click OK. Select each file and choose the Analyze Source File command from the Analyze menu. Check the Output window for successful completion. Save the HDL workspace and close the HDL Manager window.
   Note: SpeedWave can only simulate configurations. You must have at least one configuration in your testbench.
5. Select a configuration to simulate. Choose the Load Design command from the File menu. Double-click “user.lib” and select the configuration you want to simulate. Click OK. A Source Viewer window and a Hierarchy Viewer window are displayed.
6. Simulate your design. Choose the Run Simulation command from the Simulate menu. The Run Simulation dialog box is displayed. Select the desired options and click the Apply button. Click the Close button when you have completed your simulation.