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Innoveda eProduct Designer Interface Guide - UNIX
7.4
Actel-Mentor Graphics ePd Design Considerations
7.4.5
Buried I/O cores
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1
FlashROM, Analog System Builder, and Flash Memory System Builder
2
Analog System Builder, FlashROM and Flash Memory System Builder
3
ChipEditor
4
Designer Documentation Catalog
5
Libero IDE
6
Design Constraints for Software
7
Innoveda eProduct Designer Interface Guide - UNIX
7
Introduction
7.1
About this Document
7.2
Setup
7.3
Actel-Mentor Graphics Design Flow
7.4
Actel-Mentor Graphics ePd Design Considerations
7.4.1
Schematic Naming Conventions
7.4.2
Adding Power and Ground
7.4.3
Adding Pins to the Design
7.4.4
Generating a Top-Level Symbol
7.4.5
Buried I/O cores
7.4.6
Sheets and Symbols
7.4.7
Assigning Pins in a Schematic
7.4.8
Adding SmartGen Cores
7.4.9
Generating an EDIF Netlist
7.4.10
Generating a Structural VHDL Netlist
7.5
Simulation Using ViewSim
7.6
Simulation Using SpeedWave
7.7
Revision History
7
Microchip FPGA Support
7
Microchip Information
8
Innoveda eProduct Designer Interface Guide – Windows
9
FlashPro for Software
10
SmartGen Cores Reference
11
HDL Coding Style
12
Libero IDE Documentation Catalog
13
Libero IDE
14
Antifuse Macro Library Guide for Software
15
MultiView Navigator
16
NetlistViewer (non-MVN)
17
IGLOO, ProASIC3, SmartFusion and Fusion Macro Library for Software
18
ProASIC and ProASIC PLUS Macro Library for Software
19
PinEditor (non-MVN)
20
SmartPower
21
SmartTime
22
Timer
23
VHDL Vital Simulation
24
Verilog Simulation
25
Technical Support
26
About Microchip
7.4.5 Buried I/O cores
You can bury I/O cores in the design hierarchy.
Rev: A
