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Libero IDE v9.x
Libero IDE v9.x
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  2. 5 Libero IDE
  3. 5.26 Device Selection
  4. 5.26.14 Setting Compile Options
  5. 5.26.14.1 Compile options vary according to family.
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  • 1 FlashROM, Analog System Builder, and Flash Memory System Builder
  • 2 Analog System Builder, FlashROM and Flash Memory System Builder
  • 3 ChipEditor
  • 4 Designer Documentation Catalog
  • 5 Libero IDE
    • 5.1 What's New in Libero IDE v9.1
    • 5.2 Supported Families
    • 5.3 Project Management
    • 5.4 Project Files
    • 5.5 Project Options
    • 5.6 Settings
    • 5.7 Preferences
    • 5.8 Project Manager Interface
    • 5.9 Designing with Designer Block Components
    • 5.10 Creating a Designer Block Component in Libero IDE
    • 5.11 Creating a Designer Block Component in Designer
    • 5.12 Instantiating a Designer Block Component in Designer
    • 5.13 SmartDesign
    • 5.14 Getting Started with SmartDesign
    • 5.15 SmartDesign User Interface
    • 5.16 Canvas View
    • 5.17 Grid
    • 5.18 Instance-Instance View
    • 5.19 Schematic View
    • 5.20 Creating a SmartDesign
    • 5.21 Connecting Instances
    • 5.22 Bus Interfaces
    • 5.23 Incremental Design
    • 5.24 Reference
    • 5.25 Welcome to Designer
    • 5.26 Device Selection
      • 5.26.1 Device Selection Wizard
      • 5.26.2 Setting Die, Package, Speed, and Voltage
      • 5.26.3 Device Variations
      • 5.26.4 Setting Operating Conditions
      • 5.26.5 Changing Design name and family
      • 5.26.6 Changing device information
      • 5.26.7 Importing Source Files
      • 5.26.8 Importing Source Files – Copying Files Locally
      • 5.26.9 Auditing Files
      • 5.26.10 Importing auxiliary files
      • 5.26.11 Merge SDC File(s) with Existing Timing Constraints
      • 5.26.12 Merge PDC file(s) with existing physical constraints
      • 5.26.13 Compiling your design
      • 5.26.14 Setting Compile Options
        • 5.26.14.1 Compile options vary according to family.
      • 5.26.15 IGLOO, ProASIC3, SmartFusion, and Fusion Compile Options
      • 5.26.16 ProASIC and ProASIC PLUS Compile Options
      • 5.26.17 Axcelerator Compile Options
      • 5.26.18 MX, SX, SX-A, eX Compile Options
    • 5.27 Design Constraints
    • 5.28 Families Supported
    • 5.29 Entering Constraints
    • 5.30 Running Layout
    • 5.31 Device Programming
    • 5.32 Generating Programming Files
    • 5.33 TCL Command Reference
    • 5.34 Project Manager Tcl Commands
    • 5.35 Reference
    • 5.36 Dialog Boxes
    • 5.37 Revision History
    • 5 Microchip FPGA Support
    • 5 Microchip Information
  • 6 Design Constraints for Software
  • 7 Innoveda eProduct Designer Interface Guide - UNIX
  • 8 Innoveda eProduct Designer Interface Guide – Windows
  • 9 FlashPro for Software
  • 10 SmartGen Cores Reference
  • 11 HDL Coding Style
  • 12 Libero IDE Documentation Catalog
  • 13 Libero IDE
  • 14 Antifuse Macro Library Guide for Software
  • 15 MultiView Navigator
  • 16 NetlistViewer (non-MVN)
  • 17 IGLOO, ProASIC3, SmartFusion and Fusion Macro Library for Software
  • 18 ProASIC and ProASIC PLUS Macro Library for Software
  • 19 PinEditor (non-MVN)
  • 20 SmartPower
  • 21 SmartTime
  • 22 Timer
  • 23 VHDL Vital Simulation
  • 24 Verilog Simulation
  • 25 Technical Support
  • 26 About Microchip

5.26.14.1 Compile options vary according to family.

  • IGLOO, Fusion, and ProASIC3
  • ProASIC, ProASIC PLUS
  • Axcelerator
  • MX, SX, SX-A, eX

Rev: A

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