23.4.3 Timing Simulation

To perform timing simulation:

1. If you have not done so, back-annotate your design and create your testbench.

2. To perform a timing simulation using your V-System or ModelSim simulator, compile your VHDL design and testbench files, if they have not already been compiled for a structural simulation, and run a simulation. The following commands demonstrate how to compile VHDL design and testbench files:

   vcom -just e -93 <structural>.vhd

   vcom -just a -93 <structural>.vhd

   vcom <test_bench>.vhd

   Important: Performing the previous steps compiles the entities first and then the architectures, as required for VHDL netlists written by some tools.
3. Run the back-annotation simulation using the timing information in the SDF file. Type:vsim -sdf[max|typ|min] /<region>=<design name>.sdf -c

   <configuration_name>

The <region> option specifies the region (or path) to an instance in a design where back annotation begins. You can use it to specify a particular FPGA instance in a larger system design or testbench that you wish to back annotate. For example:

vsim -sdfmax /uut=adder.sdf -c test_adder_structural

In this example, the entity adder has been instantiated as instance “uut” in the testbench. The entity-architecture pair specified by the configuration named “test_adder_structural” in the testbench will be simulated using the maximum delays specified in the SDF file.

If your design contains a PLL core, use a 1ps resolution:

vsim -t ps -sdf[max|typ|min] /<region>=<design name>.sdf -c

<configuration_name>

For example:

vsim -t ps -sdfmax /uut=adder.sdf -c test_adder_structural