23.4.2 Structural Simulation

Use the following procedure to perform structural simulation.

  1. Generate a structural VHDL netlist. If you are using Synopsys Design Compiler, generate a structural VHDL netlist using this tool.

    If you are using other synthesis tools, generate a gate-level VHDL from your EDIF netlist by using the file generated automatically in your project. Some design families enable you to generate the files directly from the Tools > Export > Netlist menu.

    Important: The generated VHDL uses std_logic for all ports. The bus ports will be in the same bit order as they appear in the EDIF netlist.
  2. Map to the VITAL library. Run the following command to map the compiled VITAL library. vmap <vhd_fam> $ALSDIR\lib\vtl\95\mti\<vhd_fam>

  3. Compile the structural netlist. Compile your VHDL design and testbench files. The following commands demonstrate how to compile VHDL design and testbench files:

    vcom -just e -93 <structural>.vhd

    vcom -just a -93 <structural>.vhd

    vcom <test_bench>.vhd
    Important: First, the application compiles the entities. Then, it compiles the architectures, as required for VHDL netlists written by some tools.
  4. Run the structural simulation. To simulate your design, type:

vsim <configuration_name>

For example:

vsim test_adder_structure

The entity-architecture pair specified by the configuration named test_adder_structure in the testbench will be simulated.

If your design contains a PLL core, use a 1ps resolution:

vsim -t ps <configuration_name>

For example:

vsim -t ps test_adder_structure