23.4.1 Behavioral Simulation

Use the following procedure to perform a behavioral simulation of a design. Refer to the documentation included with your simulation tool for additional information about performing behavioral simulation.

  1. Invoke your ModelSim simulator. (PC only)
  2. Change directory to your project directory. This directory must include your VHDL design files and testbench. Type: cd <project_dir>
  3. Map to the Library. If any cores are instantiated in your VHDL source, type the following command to map them to the compiled VITAL library: vmap <vhd_fam> $ALSDIR\lib\vtl\95\mti\<vhd_fam>

    To reference the family library in your VHDL design files, add the following lines to your VHDL design files:

    library <vhd_fam>;

    use <vhd_fam>.components.all;
  4. Create a “work” directory. Type:

    vlib work

  5. Map to the “work” directory. Type the following command:

    vmap work .\work

  6. Perform a behavioral simulation of your design. To perform a behavioral simulation using your V-System or ModelSim simulator, compile your VHDL design and testbench files and run a simulation. For hierarchical designs, compile the lower-level design blocks before the higher level design blocks.

The following commands demonstrate how to compile VHDL design and testbench files:

vcom -93 <behavioral>.vhd

vcom -93 <test_bench>.vhd

To simulate the design, type:

vsim <configuration_name>

For example:

vsim test_adder_behave

The entity-architecture pair specified by the configuration named test_adder_behave in the testbench will be simulated. If your design contains a PLL core, use a 1ps resolution:

vsim -t ps <configuration_name>

For example:

vsim -t ps test_adder_behave