5.4.5 Mixed-HDL Support in Libero IDE

You must have ModelSim PE or SE to use mixed HDL in the Libero IDE. Also, you must have Synplify Pro to synthesize a mixed-HDL design.

When you create a project, you must select a preferred language. The HDL files generated in the flow (such as the post-layout netlist for simulation) are created in the preferred language.

The language used for simulation is the same language as the last compiled testbench. (E.g. if tb_top is in verilog,

<fam>.v is compiled.)

If your preferred language is Verilog, the post-synthesis and post-layout netlists are in Verilog 2001. You cannot import these netlists back into Designer; the Designer reader only accepts Verilog 95.