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Libero IDE v9.x
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22
Timer
22.16
Timing Results
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SmartTime
22
Timer
22
Welcome to Timer
22.1
Timer User Interface
22.2
Summary Tab
22.3
Timer Expanded Path Window
22.4
Clocks Tab
22.5
Paths Tab
22.6
Breaks Tab
22.7
Timer Preferences
22.8
Timer Menu Commands
22.9
Timing Report Dialog Box
22.10
Determining your Clock Frequency
22.11
Adding and Removing Break Points
22.12
Setting Preferences in Timer
22.13
Path Analysis
22.14
Specifying Timing Constraints
22.15
Constraint Guidelines
22.16
Timing Results
22.16.1
Export Results
22.16.2
Generate Reports
22.16.3
Violations Report
22.17
Keyword Filters
22.18
Calculating Delays
22.19
Using Chip Planner/ChipEditor with Timer
22.20
Timer Tcl Commands
22.21
Timing Delay Constraint Definitions
22.22
Glossary of Terms
22.23
Revision History
22
Microchip FPGA Support
22
Microchip Information
23
VHDL Vital Simulation
24
Verilog Simulation
25
Technical Support
26
About Microchip
22.16 Timing Results
Rev: A
