22.14 Specifying Timing Constraints

Timer enables you to specify timing constraints and requirements for clocks and paths. These constraints are used in timing driven layout and in timing analysis. In order to run timing driven layout, you must import an SDC or invoke timer in pre-layout mode and enter the constraints in timer GUI. Commit the changes before exiting timer.

For ProASIC, ProASIC^PLUS, and ProASIC3/E, Microchip recommends that you use timing constraints set through the SDC import or Timer GUI. For Axcelerator, you can run timing driven place-and-route even if you have not set any user constraints.

The following table shows the correlation between SDC and Timer GUI:

Table 22-1. Correlation between SDC and Timer GUI
	SDC	Timer GUI
create_clock	with waveform	with duty cycle
set_max_delay	X	X
set_multicycle_path	X	N/A
set_false_path	X	X
set load	X	N/A
clock_exception	N/A	X

Note: Timer supports set_false_path -through only. Although an SDC file allows set_false_path with combination of -from, -to and -through arguments, the tool ignores the constraint if it is not a -through only. The from or to arguments cannot be set in the Timer GUI. The set_multicycle_path constraint cannot be set in the Timer GUI; it can be set only through SDC.

You can set the load on a port using the I/O Attribute Editor.

For details on how to set the timing constraints for ProASIC ^PLUS family, see ProASIC ^PLUS Timing Closure in Libero application note.