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15.15
Dialog Boxes
15.15.12
Block Port Properties Dialog Box
15.15.12.3
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15.1
Getting Started
15.2
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15.3
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15.4
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15.5
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15.6
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15.7
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15.8
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15.9
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15.10
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15.11
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15.12
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15.13
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15.14
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15.15
Dialog Boxes
15.15.1
Assign Instances to Regions Dialog Box
15.15.2
Assign Nets to Regions Dialog Box
15.15.3
ChipPlanner Properties Dialog Box
15.15.4
Create or Edit Active Lists Dialog Box
15.15.5
I/O Bank Settings Dialog Box (IGLOO and ProASIC3 only)
15.15.6
I/O Bank Settings Dialog Box
15.15.7
More I/O Bank Attributes Dialog Box
15.15.8
Logic Instance Properties Dialog Box
15.15.9
More Active Lists Dialog Box
15.15.10
Net Properties Dialog Box
15.15.11
Path Properties Dialog Box
15.15.12
Block Port Properties Dialog Box
15.15.12.1
Name
15.15.12.2
Net
15.15.12.3
Direction
15.15.12.4
Fanout
15.15.12.5
Connections
15.15.13
PinEditor Properties Dialog Box
15.15.14
Pin List Dialog Box
15.15.15
Region Properties Dialog Box
15.15.16
Reserve Pins for Migration Dialog Box
15.15.17
Routing Details Dialog Box
15.15.18
Designer Block Properties Dialog Box
15.16
Revision History
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Microchip FPGA Support
15
Microchip Information
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NetlistViewer (non-MVN)
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IGLOO, ProASIC3, SmartFusion and Fusion Macro Library for Software
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SmartPower
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SmartTime
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Timer
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VHDL Vital Simulation
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Verilog Simulation
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Technical Support
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About Microchip
15.15.12.3 Direction
Indicates whether the block port is an input, output, or InOut port
Rev: A
