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Libero IDE v9.x
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15
MultiView Navigator
15.7
Floorplanning
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FlashROM, Analog System Builder, and Flash Memory System Builder
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Analog System Builder, FlashROM and Flash Memory System Builder
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4
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6
Design Constraints for Software
7
Innoveda eProduct Designer Interface Guide - UNIX
8
Innoveda eProduct Designer Interface Guide – Windows
9
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11
HDL Coding Style
12
Libero IDE Documentation Catalog
13
Libero IDE
14
Antifuse Macro Library Guide for Software
15
MultiView Navigator
15
Overview
15.1
Getting Started
15.2
Hierarchy Window
15.3
NetlistViewer
15.4
PinEditor
15.5
I/O Attribute Editor
15.6
ChipPlanner
15.7
Floorplanning
15.7.1
About Floorplanning
15.7.2
Floorplanning a Designer Block
15.7.3
About Regions
15.7.4
Creating Regions
15.7.5
Using Empty Regions
15.7.6
Using Logic Regions
15.7.7
Using Local Clock and Quadrant Clock Regions
15.7.8
Editing Regions
15.7.9
Assigning a Macro to a Region
15.7.10
Assigning a Net to a Region
15.7.11
Unassigning a Macro from a Region
15.7.12
Creating Local Clock Regions
15.7.13
Renaming a Local Clock Region
15.7.14
About Quadrant Clocks
15.7.15
Creating Quadrant Clock Regions
15.7.16
Assigning a Clock to a QuadrantClock Region
15.7.17
Locking Quadrant Clock Regions
15.7.18
Assigning Logic to Locations
15.7.19
Unassigning All Logic from a Location
15.7.20
Moving Logic to Other Locations
15.7.21
Locking Logic to Locations
15.8
Block Ports
15.9
Viewing Resources
15.10
Using I/O Banks
15.11
Using Active Lists
15.12
Reference
15.13
Hierarchy Window
15.14
Menus, Toolbar Buttons, and Shortcut Keys
15.15
Dialog Boxes
15.16
Revision History
15
Microchip FPGA Support
15
Microchip Information
16
NetlistViewer (non-MVN)
17
IGLOO, ProASIC3, SmartFusion and Fusion Macro Library for Software
18
ProASIC and ProASIC PLUS Macro Library for Software
19
PinEditor (non-MVN)
20
SmartPower
21
SmartTime
22
Timer
23
VHDL Vital Simulation
24
Verilog Simulation
25
Technical Support
26
About Microchip
15.7 Floorplanning
Rev: A
