11.4.10.2 SmartGen FIFO

The RAM cells in the DX and MX families can be used to implement a variety of FIFOs. The behavioral description of a 32x8 FIFO for simulation is shown below. However, most synthesis tools cannot infer technology specific features such as RAM cells. Synthesizing this model will result in high area utilization. SmartGen can generate an area and performance optimized structured HDL netlist for instantiation. Using SmartGen, generate a 32x8 FIFO with the configuration shown in Figure. Save it as a Verilog or VHDL netlist called “fifo_ff_ef.”

Figure 11-45. 32x8 FIFO
VHDL
library IEEE;
use IEEE.std_logic_1164.all;
entity fifo_32_8 is
port (D : in std_logic_vector(7 downto 0);
OUT : out std_logic_vector(7 downto 0);
Reset : in std_logic;
Rd_En, Wr_En : in std_logic;
Rd_En_F, Wr_En_F : in std_logic;
clk : in std_logic;
E_Flag, F_Flag : out std_logic);
end fifo_32_8;
architecture fifo_arch of fifo_32_8 is
component fifo_ff_ef
generic (width : integer;
depth : integer;
clrPola : integer;
clkEdge : integer);
port (Data : in std_logic_vector (width-1 downto 0);
Aclr : in std_logic;
WE : in std_logic ;
WEF : in std_logic ;
RE : in std_logic ;
REF : in std_logic ;
Clock : in std_logic ;
Q :out std_logic_vector (width-1 downto 0);
FF : out std_logic;
EF : out std_logic);
end component;
begin
F_32_8: fifo_ff_ef
generic map (width => 8, depth => 32, clrPola => 1,
clkEdge => 1)
port map (Data => D,
Aclr => Reset,
WE = > We_En,
WEF => We_En_F,
RE => Rd_En,
REF => Rd_En_F,
Clock => CLK,
Q => OUT,
FF => F_Flag,
EF => E_Flag);
end fifo_arch;
Verilog
module fifo_32_8 (D, OUT, Reset, Rd_En, Wr_En, CLK, E_Flag,
Rd_En_F, Wr_En_F, F_Flag);
input [7:0] D;
output [7:0] OUT;
input Reset;
input Rd_En;
input Rd_En_F;
input Wr_En;
input Wr_En_F;
input CLK;
output E_Flag;
output F_Flag;
wire [7:0] OUT;
wire E_Flag;
wire F_Flag;
fifo_ff_ef F_32_8 (.Data(D), .Aclr(Reset), .WE(Wr_En),
.WEF(Wr_En_F), .RE(Rd_En), .REF(Rd_En_F)
.Clock(CLK), .Q(OUT), .FF(F_Flag), .EF(E_Flag));
endmodule