11.2.5.1 Tri-State Buffer

A tri-state buffer is an output buffer with high-impedance capability. The following examples show how to infer and instantiate a tri-state buffer.

Figure 11-18. Tri-State Buffer

Inference

VHDL
library IEEE;
use IEEE.std_logic_1164.all;
entity tristate is
port (e, a : in std_logic;
y : out std_logic);
end tristate;
architecture tri of tristate is
begin
process (e, a)
begin
if e = '1' then
y <= a;
else
y <= 'Z';
end if;
end process;
end tri;

or

library IEEE;
use IEEE.std_logic_1164.all;
entity tristate is
port (e, a : in std_logic;
y : out std_logic);
end tristate;
architecture tri of tristate is
begin
Y <= a when (e = '1') else 'Z';
end tri;
Verilog
module TRISTATE (e, a, y);
input a, e;
output y;
reg y;
always @ (e or a) begin
if (e)
y = a;
else
y = 1'bz;
end
endmodule

or

module TRISTATE (e, a, y);
input a, e;
output y;
assign y = e ? a : 1'bZ;
endmodule

Instantiation

VHDL
library IEEE;
use IEEE.std_logic_1164.all;
entity tristate is
port (e, a : in std_logic;
y : out std_logic);
end tristate;
architecture tri of tristate is
component TRIBUFF
port (D, E: in std_logic;
PAD: out std_logic);
end component;
begin
U1: TRIBUFF port map (D => a,
E => e,
PAD => y);
end tri;
Verilog
module TRISTATE (e, a, y);
input a, e;
output y;
TRIBUFF U1 (.D(a), .E(e), .PAD(y));
endmodule