11.2.5.2 Bi-Directional Buffer

A bi-directional buffer can be an input or output buffer with high impedance capability. The following examples show how to infer and instantiate a bi-directional buffer.

Inference

VHDL

library IEEE;
use IEEE.std_logic_1164.all;
entity bidir is
port (y : inout std_logic;
e, a: in std_logic;
b : out std_logic);
end bidir;
architecture bi of bidir is
begin
process (e, a)
begin
case e is
when '1' => y <= a;
when '0' => y <= 'Z';
when others => y <= 'X';
end case;
end process;
b <= y;
end bi;

Verilog

module bidir (e, y, a, b);
input a, e;
inout y;
output b;
reg y_int;
wire y, b;
always @ (a or e)
begin
if (e == 1'b1)
y_int <= a;
else
y_int <= 1'bz;
end
assign y = y_int;
assign b = y;
endmodule

Instantiation

VHDL

library IEEE;
use IEEE.std_logic_1164.all;
entity bidir is
port (y : inout std_logic;
e, a: in std_logic;
b : out std_logic);
end bidir;
architecture bi of bidir is
component BIBUF
port (D, E: in std_logic;
Y : out std_logic;
PAD: inout std_logic);
end component;
begin
U1: BIBUF port map (D => a,
E => e,
Y => b,
PAD => y);
end bi;

Verilog

module bidir (e, y, a, b);
input a, e;
inout y;
output b;
BIBUF U1 ( .PAD(y), .D(a), .E(e), .Y(b) );
endmodule