11.4.3.4 Asynchronous Preset and Clear

This is the most problematic register for the ACT2, XL, DX, MX, SX and ACT3 architectures. You can only use one cell (the DFPC cell) to design an asynchronous preset and clear register. The DFPC uses two CMODs to form a master latch and a slave latch that together form one register. This uses two CMODs per register and offers no logic combinability with the SMOD. The DFPC requires more setup time and no combinability. The net timing loss can often be as high as 10ns. Microchip recommends that you do not use any asynchronous preset and clear registers on critical paths. Use a synchronous preset with asynchronous clear or a synchronous clear register instead. You can use an asynchronous preset and clear register if it does not affect a critical path or cause high utilization in the design.