24.2.2.2 Design Implementation

During design implementation, you place-and-route a design using Designer. Additionally, you can perform static-timing analysis on a design in Designer with the Timer tool. After place-and-route, you can perform postlayout (timing) simulation with a Verilog simulator.

Place-and-Route:

Use Designer to place-and-route your design. Make sure to specify Verilog as the Naming Style when importing the EDIF netlist into Designer. Refer to the Designer User’s Guide for information about using Designer.

Static-Timing Analysis

Use the Timer tool in Designer to perform static-timing analysis on your design. Refer to the Timer User’s Guide for information about using Timer.

Timing Simulation

Perform a timing simulation of your design after placing-and-routing it. Timing simulation requires information extracted from Designer, which overrides default unit delays in the Microchip Verilog libraries. Refer to “Timing Simulation” and the documentation included with your simulation tool for information about performing timing simulation.