24.2.2.1 Design Creation/Verification

During design creation/verification, a design is captured as a schematic or as an RTL-level (behavioral) Verilog HDL source file.

If your design is a Verilog HDL source file, you can perform a behavioral simulation to verify that the HDL code is correct. The code is then synthesized into an Microchip gate-level (structural) Verilog HDL netlist. After synthesis, you can perform a structural simulation of the design. Finally, you generate an EDIF netlist for use in Designer and a structural Verilog netlist for structural and timing simulation.

If your design is a schematic, you generate an EDIF netlist for use in Designer and a structural Verilog netlist for structural and timing simulation. You do not perform behavioral simulation or synthesis.

Design Capture

Enter your schematic using a third-party schematic-capture tool or create your Verilog HDL source file using a text editor or a context-sensitive HDL editor. Your Verilog HDL design source can contain RTL-level constructs, as well as instantiations of structural elements, such as SmartGen cores. Refer to the documentation included with your design-capture tool for information about design capture.

Behavioral Simulation

Perform a behavioral simulation of your design before synthesis. Behavioral simulation verifies the functionality of your Verilog HDL code. You can use a standard Verilog HDL testbench to drive simulation. Refer to “Behavioral Simulation” and the documentation included with your simulation tool for information about performing functional simulation.

Synthesis

After you have created your Verilog HDL source file, you must synthesize it before placing-and-routing it in Designer. Synthesis transforms the Verilog HDL source file into a gate-level netlist and optimizes the design for a target technology. Refer to the documentation included with your synthesis tool for information about performing design synthesis.

EDIF Netlist Generation

After you have created, synthesized (if your design is an HDL source file), and verified your design, you must generate an EDIF netlist or import verilog netlists for place-and-route in Designer. If your design is a Verilog HDL source file, use the EDIF netlist to generate a structural Verilog netlist.

Refer to “Generating an EDIF Netlist” and the documentation included with your schematic-capture or synthesis tool for information about generating an EDIF netlist.

Structural Verilog Netlist Generation

Generate a structural Verilog netlist from your EDIF netlist for use in structural and timing simulation by either exporting it from Designer or by using the Microchip “edn2vlog” program. Refer to “Generating a Structural Verilog Netlist” for information about generating a structural netlist.

Structural Simulation

Perform a structural simulation of your design before placing-and-routing it. Structural simulation verifies the functionality of your structural Verilog netlist. Use default unit delays included in the Verilog libraries for every gate. Refer to “Structural Simulation” and the documentation included with your simulation tool for information about performing structural simulation.