3.4.3.6 RSSI Buffer

RSSI Buffer Overview

The RSSI buffer module provides an averaged RSSI (received signal strength indication) value, a peak RSSI value and two flags indicating a failure or a success of the RSSI range check. Peak or average values can be collected in the SFIFO for bulk readout. The following figure shows a block diagram of the RSSI buffer.
Figure 3-15. RSSI Buffer Block Diagram

The ASK demodulator provides a raw RSSI signal that is used as input for the average and peak value calculations. The averaging period can be set by the RSSC.RSUP register. A single RSSI value is forwarded after every averaging period. The peak detection forwards the maximum value within one averaging period. A four-sample smoothening of the raw RSSI data stream is used during the peak value detection.

Before the average and peak values are written to the RRSAV and RSSPK registers, an internal gain compensation eliminates different gains for High-Band reception, Low-Band reception and IF amplifier activation to generate accurate and comparable RSSI values.

The following registers must be correctly configured to adjust the gain compensation:

  • RSSC.RSHRX: Low-Band/High-Band selection
  • RSCOM.RSIFC: IF amplifier ON/OFF
  • RSCOM.RSDC: Antenna damping ON/OFF
  • RSIFG: Compensation value for IF amplifier
  • RSLDV: Compensation value for antenna damping Low-Band
  • RSHDV: Compensation value for antenna damping High-Band

The gain-compensated RSSI values are finally written to the 16-byte deep SFIFO. RSSC.RSPKF selects whether the average or the peak values are used. The values can be read from the SFIFO via SPI.

The RSSI buffer contains an additional RSSI range check that generates an RSSI range OK signal and an RSSI range fail signal when the RSSI measurement is used as a signal check. A window can be defined by the RSSL and RSSH register and, depending on the RSSC.RSWLH setting, the current RSSI value must be inside or outside the defined window for a successful check. The RSSI buffer is reset when activated in the corresponding PRR2.PRRS power reduction register (see Sleep Modes and Active Power Reduction).

If not stated otherwise, a detailed description of the required register bits is found in the section RSSI Buffer Register Description.
Figure 3-16. RSWLH Working Principle