3.4.3.3 Frame Synchronizer

The frame synchronizer block analyzes the demodulated data and compares it to the configured pattern to detect a valid preamble and the start point of a telegram within the data stream.

The frame synchronizer works on a symbol basis. All registers configure and refer to data symbols, not data bits. Please refer to NRZ and Manchester Coding for hints on “bits” and “symbols.”

The complete hardware is available twice to allow separate configuration and processing of path A and path B. In the following sections, a small x indicates that the description is valid for both paths.

The frame synchronizer is reset at every demodulator restart.

If not stated otherwise, a detailed description of the required register bits is found in Frame Synchronizer Register Description.

Pattern Correlation

Two different patterns, each with a length of up to 32 symbols, can be defined to implement a customized wake check OK (WCO) and start of telegram (SOT) detection procedure.

An example for the correlation process and the pattern match generation for one path is visualized in the following figure.

Figure 3-9. WUP and SFID Pattern Correlator

The demodulated symbol stream is checked in parallel for the configured wake-up pattern (WUP) and start frame identification (SFID). A pattern match is signaled by setting the corresponding SOTSx.WUPOx or SOTSx.SFIDOx bit to ‘1’ (for more information, see RX DSP Control Register Description).

The WUP can be configured on a symbol basis in the WUP4x, WUP3x, WUP2x and WUP1x registers. The SFID pattern can be configured on a symbol basis in the SFID4x, SFID3x, SFID2x and SFID1x registers.

The length of each pattern is configurable between 1 and 32 symbols in WUPLx and SFIDLx. If the length of the pattern is configured to be less than 32, the corresponding number of least significant symbols are selected and the rest is ignored.

To create a pattern match, the number of matching symbols has to exceed the threshold values in WUPTx and SFIDCx.SFIDTx. Thus, if the complete pattern is supposed to match, the threshold value has to be one less than the pattern length value.

To avoid an unintended early WUP or SOT, a pattern match will only be indicated if at least the number of symbols configured in the length register was received. Any earlier pattern match is suppressed.

The SIFDCx.SEMEx serial mode enable bit can be used to activate a hardware suppression of an SFID match until a WUP match occurs and a full SFID pattern is received after the WUP.

The data polarity can be configured in DMMx.DMPx (see Demodulator Register Description). If DMPx = 1, the received data are inverted in the demodulator before they are transferred to the correlator. Therefore, the configured WUP and SFID pattern must be the inverse of the RF signal.

Configuration example for a wake-up and SFID pattern on path A:

DMMA.DMNEA = 0 Data are Manchester-coded

DMMA.DMPA = 1 Manchester polarity: Falling edge in the middle of a bit is ‘1’, data are inverted in the demodulator

WUP4A = 0x80

WUP3A = 0x00

WUP2A = 0x66

WUP1A = 0x66 -> WUP= 1000 0000 0000 0000 0110 0110 0110 0110

WUPLA = 8 -> Only eight LSBs of WUP are considered (0x66) WUPTA = 7 -> Threshold = WUPTA+1 -> All eight symbols must match

SFID4A = 0x00

SFID3A = 0x00

SFID2A = 0x55

SFID1A = 0xA6 -> SFID = 0000 0000 0000 0000 0101 0101 1010 0110