3.4.3.8 RX DSP Control

The RX DSP control block contains the high level control and status signals of the RX DSP.

A fixed sequence has to be observed when the RX path is enabled. This is normally done by the firmware. The procedure to enable the RX DSP path from the reset state is:

  1. Start the channel filter.
    1. Set the channel filter configuration
      1. CHDN(ADCDN, BBDN) register
      2. CHCR(BWM) register
    2. Enable CLKADIV if required RDCR.ADIVEN = [1|0]
    3. RDCR.RDPU = 1; enable the RX DSP power
    4. Wait 200 ns for the power supply settling
    5. RDCR.RDEN = 1; enable the RX DSP receive path
    6. RDPR.PRFLT = 0; enable channel filter operation
    7. Wait for the channel filter settling time
  2. Start the demodulator.
    1. Set the demodulator configuration (can also be set at 1.a)
    2. RDPR.PRPTA/B = 0; enable demodulator
  3. RX DSP is operational.

Wake Check OK

The “Wake Check OK” (WCO) signal provides a flexible means for detecting a valid preamble signal. Up to seven checks can be activated as a condition for a successful wake check (WCOA/B).

The following figure shows the logic structure of the wake check for receiving path A.

Path B is identical except for the signal name endings which must be replaced by a “B”.
Figure 3-18. WCOA Logic

Each enable signal (ending with ..EA) activates the corresponding condition. For example, CAROEA = 1 activates the CAROA (“Carrier Check OK on Path A”) signal as a necessary condition for WCOA to become 1. If a check is not activated (e.g., CAROEA = 0), it is considered successful from the beginning. All activated checks have to be true to set the WCOA register (not shown in the preceding figure).

For further details about the activation of the conditions, see the SOTCA/B register description. A detailed explanation of the actual signal checks is found at the register description of the SOTSA/B registers. The handling of the WCOA/B flag is described in the RDSIFR register. For all register descriptions, see RX DSP Control Register Description.

Start of Telegram

The “Start of Telegram” signal provides a flexible means of detecting a valid preamble signal. Up to eight checks can be activated as a condition for a successful start of the telegram check (SOTA/B). The start of telegram conditions are the same as the wake check OK conditions with the additional SFIDOA check.

The following figure shows the logic structure of the start of the telegram check for the receiving path A. Path B is identical except for the signal name endings, which must be replaced by a “B”.
Figure 3-19. SOTA Logic

Each enable signal (ending with ..EA) activates the corresponding condition. For example, SFIDOEA = 1 activates the SFIDOA (“Start Frame ID OK on Path A”) signal as a necessary condition for SOTA to become 1. If a check is not activated (e.g., SFIDOEA = 0), it is considered successful from the beginning. All activated checks have to be true to set the SOTA register (not shown in the preceding figure).

For further details about the activation of the conditions, see the SOTCA/B register description. A detailed explanation of the actual signal checks is found at the register description of the SOTSA/B registers. The handling of the SOTA/B flag is described in the RDSIFR register. For all register descriptions, see RX DSP Control Register Description.

End of Telegram

The “End of Telegram” signal provides a flexible means of detecting an invalid signal or the end of a telegram. Up to eight checks can be activated to indicate an invalid signal (EOTA/B).

The following figure shows the logic structure of the end of the telegram check for the receiving path A. Path B is identical except for the signal name endings, which must be replaced by a “B”.
Figure 3-20. EOTA Logic

Each enable signal (ending with ..EA) activates the corresponding condition. For example, MANFEA = 1 activates the MANFA (“Manchester Coding Conformity Check Failure on Path A”) signal as a necessary condition for EOTA to become ‘1’. If a check is not activated (e.g., MANFEA = 0), it is ignored from the beginning. Each activated check alone can trigger the EOTA register (not shown in the preceding figure.)

For further details about the activation of the conditions, see the EOTCA register. A detailed explanation of the actual signal checks is found at the register description of the EOTSA registers. The handling of the EOTA/B flag is described in the RDSIFR register. For all register descriptions, see RX DSP Control Register Description.