3.4.3.4 RX Buffer

RX Buffer Overview

The RX buffer uses the demodulated serial data stream from the RX-DSP as input. The input data are synchronized to the AVR clock domain and strobed to an 8-bit shift register. Then, the data is automatically written byte-wise from the shift register to the DFIFO and the ID check module (if enabled). The data order can be selected to be MSB-first or LSB-first in the RXBC1.RXMSBA/B register. Additionally, a CRC checksum can be calculated on the received data. The following figure shows a block diagram of the RX buffer.
Figure 3-11. RX Buffer Block Diagram

There are two identical RX buffer kernels available to allow a separate configuration and processing of path A and path B. In the following sections, a small x indicates that the description is valid for both paths. Upon detection of an SOT, the active path must be selected in RXBC2.RXBPB before the first byte is written to the DFIFO via the output multiplexer. In the ATA8510/15, the process is controlled by the sequencer state machine.

After SOT, any EOT event on the active path causes the sequencer state machine to set the RXBC2.RXBF finish bit. The data currently available in the shift register are immediately sent to the DFIFO correctly aligned, and, afterward, the RX buffer stops operation until it is reset. The same procedure is carried out when the telegram length is reached, which can be configured in the RXTLHx/RXTLLx registers or when the RX buffer finish bit is set in RXBC2.RXBF via the AVR bus.

The RX buffer is reset when activated in the corresponding PRR2.PRXx power reduction register (see Sleep Modes and Active Power Reduction) or by writing a ‘1’ to the RXBC2.RXBCLR bit.

If not stated otherwise, a description of the required register bits is found in RX Buffer Register Description.

Receive CRC Calculation

A cyclic redundancy check (CRC) calculation of the received payload data can be enabled independently for every path by setting RXBC1.RXCEx to ‘1’. The following figure shows a block diagram of the CRC module in 16-bit mode.
Figure 3-12. Receive CRC Block Diagram

The CRC block is implemented as a 16-bit shift register with configurable feedback loops. When the RX buffer is enabled, the CRC shift register is initialized with RXCIHx/RXCILx (default value: 0x00). The length of the shift register can be reduced to eight bits or four bits in the RXCR2.RXCBLx register for CRC8 or CRC4 calculations, respectively. The preceding figure does not show the corresponding logic.

The coefficients of the CRC polynomial can be configured in the RXCPHx/RXCPLx registers. The position in the RXCPx word corresponds to the degree of the term within the polynomial, as illustrated for a 16-bit polynomial in the following figure. The coefficient of the x0 term of a CRC polynomial must always be ‘1’, and, thus, bit 0 of RXCPLx is hard-wired to ‘1’.
Figure 3-13. Receive CRC Polynomial

A skip period can be configured in RXCSBx. If this value is greater than 0x00, the RX buffer omits the first RXCSBx bits of the payload data stream before enabling the CRC.

The current CRC result can be read in the RXCRHx/RXCRLx registers. If the CRC result is “0x0000” for an RX buffer finish event, the CRC check is considered successful and the TESRx.CRCOx register bit is written to ‘1’ (see RX Buffer Register Description).