3.4.3.2 Demodulator and Signal Checks

This section describes the demodulators and the signal checks for the receiving path A and path B. Path B is an identical copy of path A. A/B at the ending of a signal name indicates this signal is present in both paths. For example, RXFOA/B means there is an RXFOA signal in path A and an RXFOB signal in path B.

The internal states of the receiving paths A/B are reset by disabling the complete RX DSP (RDCR.RDEN = 0), by activating the power reduction for the channel filter (RDPR.PRFLT = 1) or by activating only the power reduction for the receiving A/B path (RDPR.PRPTA/B = 1).

An ASK and an FSK demodulator are available in each path. Only one of them is used for further processing. The relevant demodulator is chosen by setting the DMCRA/B.SASKA/B bit accordingly.

If not otherwise specified, a detailed description of the required register bits is found in Demodulator Register Description.

ASK Demodulation

ASK demodulation is achieved by calculating the magnitude of the complex IQ_samples from the channel filter in a logarithmic scale. Before the signal goes to the filters, it is limited to an amplitude range of 23 dB from the peak value. The ASK demodulator tolerates fading of up to 1 dB per bit.

The ASK demodulator additionally provides the raw RSSI signal, which is further processed in the RSSI buffer (see RSSI Buffer).

FSK Demodulation

The demodulator is based on a digital PLL. The demodulating process starts with the carrier frequency detection of the useful signal, which is (assumed to be) the dominant frequency within the spectrum in the channel filter.

The demodulator is centered using the measured frequency offset to the desired frequency. To do this, the time constant of the regulation loop is changed in stepwise increments. The required final effective bandwidth depends on the frequency deviation and data rate of the signal to be received and is set in the DMCRA/B.DMPGA/B register bits. Therefore, the effective noise bandwidth for the demodulation process is less than the receiver bandwidth, resulting in a higher CNR.

The maximum deviation supported by the FSK demodulator is limited by the internal sampling rate. See the Table 3-13 for limit values.

Received Frequency Offset

The offset of the actually received RF signal frequency versus the expected RF signal frequency is provided by the FSK demodulators for path A and path B. It can be read out during reception from the RXFOA/B register.

Carrier Check

The carrier check provides a means for verifying whether a carrier signal or only noise is present at the RF input. The block checks the phase difference at the phase comparator of the PLL for each input sample. The phase difference has to stay within ±90° to be valid. A phase jump outside of these boundaries indicates the dominance of noise or an unexpected signal. An error is flagged when the number of violations within a defined time interval exceeds a predefined threshold.

The severity of the signal check is determined by two settings:

• The length of the time interval where the phase jump violations are accumulated is set by the DMCDA/B.DMCTA/B register bits. The counter is reset at the end of each time window and the counting is restarted.
• The threshold for phase jump violations not triggering an error is set by the DMCDA/B.DMCLA/B register bits.

The resulting EOTSA/B.CARFA/B flag indicates the failure of the carrier check, see RX DSP Control Register Description. The SOTSA/B.CAROA/B success flag is set if the number of symbols defined by SYCA/B.SYCSA/B is received at the beginning of a telegram without the occurrence of this error.

Data Filter

The data filter contains two matched filters. One for symbol-based NRZ reception and one for Manchester-coded data. One of them can be selected for data reception by setting the DMMA/B.DMNEA/B bits.

The data filters require target data rate information for proper operation. The data rate is set by configuring the DMDRA/B registers accordingly. The data rates can be set independently for path A and path B.

The matched symbol filter generates the TRPA/B outputs and the corresponding SYMA/B signals (see Figure 3-8) for internal use. The symbol filter contains a feedback loop for DC removal. A matched filter for Manchester-coded data is provided for improved sensitivity. The filter generates the internal MANA/B signals.

The maximum symbol rate and deviation is limited by the sampling rate of the demodulator (CLK_BB) and the data filter. The sampling rate is determined by the selected channel filter bandwidth. The typical limits for an RF signal of 433.92 MHz are shown in the following table. The limits for a certain application are subject to RF signal-dependent scaling and can differ from these values by -5.6% to +3.6%. The actual limits can be calculated by multiplying the maximum symbol rate and the maximum deviation from the following table with the scaling factor (SFRQ_APPL) derived for the bandwidth scaling (Channel Filter Bandwidths).

Modulation Amplitude Check

An incoming signal is expected to have a modulation. This check verifies the modulation amplitude at the output of the data filter. The minimum for the expected signal modulation amplitude can be set in the DMMA/B.DMATA/B register. An error is flagged if the signal fails to exceed the threshold within two data symbols for the alternating preamble pattern (DMCRA.SY1TA/B = 1) or three symbols for the flexible preamble pattern (DMCRA.SY1TA/B = 0).

The EOTSA/B.AMPFA/B register bit is set to indicate the failure of this check, see RX DSP Control Register Description.

The SOTSA/B.AMPOA/B success flag is set if the number of symbols defined by SYCA/B.SYCSA/B passes at the beginning of a telegram without the occurrence of this error.

Clock Recovery

The clock recovery provides a sampling clock for the incoming data and the clock output for the TMDO_CLK pin. It is a DPLL-based circuit capable of being adapted to data rate tolerances and to ignore individual bit errors. The DPLL is more tolerant at power-up (telegram preamble), and, thus, allows for a wider data rate range. Within a few signal edges, the DPLL locks to the actual data rate and reduces the flexibility, enhancing noise immunity.

The initial data rate setting is obtained from the DMDRA/B register.

Symbol Timing Check

The symbol timing check is concerned with the timing of the signal transition from one symbol to the next. The edges of the symbols are expected to stay within some boundaries relative to the internal clock recovery. There are two settings for this check:

• The timing limit (SYCA/B.SYTLA/B) defines a validity window for the symbol edge relative to its expected location.
• The symbol check size (SYCA/B.SYCSA/B) defines the number of symbols that have to pass without an error before OK flags indicate the success of several signal checks. This is the precondition for marking an incoming signal a valid telegram by setting the RDSIFR.SOTA/B flags to high (see RX DSP Control Register Description).

The OK flags affected by this setting are:

• Carrier OK (SOTSA/B.CAROA/B)
• Modulation amplitude OK (SOTSA/B.AMPOA/B)
• Symbol timing OK (SOTSA/B.SYTOA/B)
• Manchester check OK (SOTSA/B.MANOA/B)

The EOTS.SYTFA/B bit is set to indicate the failure of this check, see RX DSP Control Register Description.

The SOTSA/B.SYTOA/B success flag is set if the number of symbols defined by SYCA/B.SYCSA/B (see SYCA) passes at the beginning of a telegram without this error occurring.

Manchester Check

The Manchester check verifies that the incoming modulation conforms with Manchester coding.

The only setting for this check is the activation of a more severe mode for the telegram start where only alternating high and low symbols are accepted as valid by the (DMCRA/B.SY1TA/B) register.

The EOTS.MANFA/B bit is set to indicate the failure of this check (for more information, see RX DSP Control Register Description).

The SOTSA/B.MANOA/B success flag is set if the number of symbols defined by SYCA/B.SYCSA/B passes at the beginning of a telegram without this error occurring.