3.10.2.3.1 SREG – Status Register


Bit	7	6	5	4	3	2	1	0
	I	T	H	S	V	N	Z	C
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 7 – I Global Interrupt Enable

The Global Interrupt Enable bit (I bit) must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the I bit is cleared, regardless of the individual interrupt enable settings none of the interrupts are enabled. The I bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I bit can also be set and cleared by the application with the SEI and CLI instructions, as described in AVR Instruction Set Summary.

Bit 6 – T Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.

Bit 5 – H Half Carry Flag

The Half Carry Flag H indicates a half carry in some arithmetic operations. Half carry is useful in BCD arithmetic. For more information, see AVR Instruction Set Summary.

Bit 4 – S Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two's Complement Overflow Flag V. For more information, see AVR Instruction Set Summary.

Bit 3 – V Two's Complement Overflow Flag

The Two's Complement Overflow Flag V supports two's complement arithmetic. For more information, see AVR Instruction Set Summary.

Bit 2 – N Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. For more information, see AVR Instruction Set Summary.

Bit 1 – Z Zero Flag

The Zero Flag Z indicates a ‘0’ result in an arithmetic or logic operation. For more information, see AVR Instruction Set Summary.

Bit 0 – C Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. For more information, see AVR Instruction Set Summary.

Name:	SREG
Offset:	0x03F
Reset:	0x00